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IDT71682LA100EB

产品描述Standard SRAM, 4KX4, 100ns, CMOS, CDFP24, 0.300 INCH, CERPACK-24
产品类别存储    存储   
文件大小84KB,共8页
制造商IDT (Integrated Device Technology)
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IDT71682LA100EB概述

Standard SRAM, 4KX4, 100ns, CMOS, CDFP24, 0.300 INCH, CERPACK-24

IDT71682LA100EB规格参数

参数名称属性值
是否Rohs认证不符合
零件包装代码DFP
包装说明0.300 INCH, CERPACK-24
针数24
Reach Compliance Codenot_compliant
ECCN代码3A001.A.2.C
最长访问时间100 ns
I/O 类型SEPARATE
JESD-30 代码R-GDFP-F24
JESD-609代码e0
长度15.748 mm
内存密度16384 bit
内存集成电路类型STANDARD SRAM
内存宽度4
功能数量1
端口数量1
端子数量24
字数4096 words
字数代码4000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织4KX4
输出特性3-STATE
可输出NO
封装主体材料CERAMIC, GLASS-SEALED
封装代码DFP
封装等效代码FL24,.4
封装形状RECTANGULAR
封装形式FLATPACK
并行/串行PARALLEL
电源5 V
认证状态Not Qualified
筛选级别38535Q/M;38534H;883B
座面最大高度2.286 mm
最大待机电流0.0001 A
最小待机电流2 V
最大压摆率0.08 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
宽度9.144 mm
Base Number Matches1

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CMOS STATIC RAMS
16K (4K x 4-BIT)
Separate Data Inputs and Outputs
Integrated Device Technology, Inc.
IDT71681SA/LA
IDT71682SA/LA
FEATURES:
• Separate data inputs and outputs
• IDT71681SA/LA: outputs track inputs during write mode
• IDT71682SA/LA: high-impedance outputs during write
mode
• High speed (equal access and cycle time)
— Military: 15/20/25/35/45/55/70/85/100ns (max.)
— Commercial: 15/20/25/35/45ns (max.)
• Low power consumption
• Battery backup operation—2V data retention (LA version
only)
• High-density 24-pin 300-mil Ceramic or Plastic DIP, 24-
pin CERPACK, and 28-pin leadless chip carrier
• Produced with advanced CMOS high-performance
technology
• CMOS process virtually eliminates alpha particle soft-
error rates
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT71681/IDT71682 are 16,384-bit high-speed static
RAMs organized as 4K x 4. They are fabricated using IDT’s
high-performance, high-reliability technology—CMOS. This
state-of-the-art technology, combined with innovative circuit
design techniques, provides a cost-effective approach for
high-speed memory applications.
Access times as fast as 15ns are available. These circuits
also offer a reduced power standby mode. When
CS
goes
HIGH, the circuit will automatically go to, and remain in, this
standby mode as long as
CS
remains HIGH. In the standby
mode, the devices consume less than 10µW, typically. This
capability provides significant system-level power and cooling
savings. The low-power (LA) versions also offer a battery
backup data retention capability where the circuit typically
consumes only 1µW operating off a 2V battery.
All inputs and outputs of the IDT71681/IDT71682 are TTL-
compatible and operate from a single 5V supply.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
ADDRESS
DECODER
A
11
16,384-BIT
MEMORY ARRAY
GND
D
4
D
3
D
2
D
1
I/O CONTROL
INPUT
DATA
CONTROL
Y
4
Y
3
Y
2
Y
1
WE
CS
IDT71682 ONLY
IDT71681 ONLY
2984 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994
Integrated Device Technology, Inc.
MAY 1994
DSC-1018/3
5.3
1

 
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