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DS1005
5-Tap Silicon Delay Line
www.dalsemi.com
FEATURES
All-silicon time delay
5 taps equally spaced
Delay tolerance ±2 ns or ±3%, whichever is
greater
Stable and precise over temperature and
voltage range
Leading and trailing edge accuracy
Economical
Auto-insertable, low profile
Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
Tape and reel available for surface-mount
Low-power CMOS
TTL/CMOS compatible
Vapor phase, IR and wave solderability
Custom delays available
Quick turn prototypes
Extended temperature range available
IN
NC
NC
TAP 2
NC
TAP 4
GND
PIN ASSIGNMENT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
NC
TAP 1
NC
TAP 3
NC
TAP 5
IN
NC
NC
TAP 2
NC
TAP 4
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
NC
TAP 1
NC
TAP 3
NC
TAP 5
DS1005 14-Pin DIP (300-mil)
See Mech. Drawings Section
DS1005S 16-Pin SOIC
(300-mil)
See Mech. Drawings Section
8
7
6
5
V
CC
TAP 1
TAP 3
TAP 5
IN
TAP 2
TAP 4
GND
1
2
3
4
DS1005M 8-Pin DIP (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1-TAP 5
V
CC
GND
NC
IN
- TAP Output Number
- +5 Volts
- Ground
- No Connection
- Input
DESCRIPTION
The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns
to 250 ns, with an accuracy of
±2
ns or
±3%,
whichever is greater. This device is offered in a standard 14-
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is
achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call (972) 371–4348.
1 of 6
111799
DS1005
LOGIC DIAGRAM
Figure 1
PART NUMBER DELAY TABLE (t
PHL
, t
PLH
)
Table 1
PART NO.
TAP 1
DS1005-60
12 ns
DS1005-75
15 ns
DS1005-100
20 ns
DS1005-125
25 ns
DS1005-150
30 ns
DS1005-175
35 ns
DS1005-200
40 ns
DS1005-250
50 ns
Custom delays available
TAP 2
24 ns
30 ns
40 ns
50 ns
60 ns
70 ns
80 ns
100 ns
TAP 3
36 ns
45 ns
60 ns
75 ns
90 ns
105 ns
120 ns
150 ns
TAP 4
48 ns
60 ns
80 ns
100 ns
120 ns
140 ns
160 ns
200 ns
TAP 5
60 ns
75 ns
100 ns
125 ns
150 ns
175 ns
200 ns
250 ns
2 of 6
DS1005
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-1.0V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
High Level Input
Voltage
Low Level Input
Voltage
Input Leakage
Current
Active Current
High Level Output
Current
Low Level Output
Current
SYM
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
0.0V
≤
V
I
≤
V
CC
V
CC
=Max;
Period=Min.
V
CC
=Min.
V
OH
=4
V
CC
=Min.
V
OL
=0.5
TEST
CONDITION
MIN
4.75
2.2
-0.5
-1.0
(0°C to 70°C; V
CC
= 5.0V ± 5%)
TYP
5.00
MAX
5.25
V
CC
+ 0.5
0.8
1.0
40
70
-1.0
12
UNITS
V
V
V
uA
mA
mA
mA
2
NOTES
1
1
1
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Pulse Width
Input to Tap Delay
(leading edge)
Input to Tap Delay
(trailing edge)
Power-up Time
SYMBOL
t
WI
t
PLH
t
PHL
t
PU
Period
MIN
40% of Tap 5 t
PLH
(T
A
= 25°C; V
CC
= 5V ± 5%)
TYP
Table 1
Table 1
100
MAX
UNITS
ns
ns
ns
ms
ns
NOTES
7
3, 4, 5, 6
3, 4, 5, 6
4 (t
WI
)
7
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
5
MAX
10
(T
A
= 25°C)
UNITS
pF
NOTES
3 of 6
DS1005
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. V
CC
= 5V @ 25°C. Delays accurate on both rising and falling edges within
±2
ns or
±3%,
whichever
is greater.
4. See Test Conditions.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of
±1.5
ns or
±4%,
whichever is greater.
6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows
down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
7. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
4 of 6
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