MK3732-07
ADSL VCXO C
LOCK
S
OURCE
Description
The MK3732-07 is a low cost, low jitter, high
performance VCXO and PLL clock synthesizer
designed to replace expensive VCXO modules and
oscillators. The on-chip Voltage Controlled Crystal
Oscillator (VCXO) accepts a 0 to 3.3 V input voltage to
cause the output clocks to vary by +100 ppm. Using
ICS’ patented VCXO and analog Phase-Locked Loop
(PLL) techniques, the device uses an inexpensive
13.248 MHz pullable crystal input to produce one or
two output clocks.
The MK3732-07 is a pin-to-pin replacement for the
MK2732-07 when using +3.3V supply voltage.
ICS manufactures the largest variety of xDSL clock
synthesizers for all applications. Consult ICS to
eliminate VCXOs, crystals, and oscillators from your
board.
Features
•
Packaged in 16 pin (150 mil) SOIC
•
Replaces a VCXO and oscillator
•
Ideal for Asymmetrical Digital Subscriber Line
(ADSL) chipsets
•
Uses an inexpensive pullable crystal
•
On-chip patented VCXO with pull range of 200 ppm
(+ 100 ppm) minimum
•
•
•
•
•
VCXO tuning voltage of 0 to 3.3 V
12 mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3V
Industrial temperature range available
Block Diagram
VDD
3
S 2 :S 0
V IN
X1
1 3 .2 4 8 M H z
P u lla b le
C ry s ta l
3
CLK1
P LL/
C lo c k
S y n th e s is
C irc u itry
CLK2
X2
V o lta g e
C o n tro lle d
C ry s ta l
O s c illa to r
3
GND
OE
MDS 3732-07 F
1
Revision 100102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK3732-07
ADSL VCXO C
LOCK
S
OURCE
Pin Assignment
Clock Select Table
S2 S1 S0
Input
13.248
13.248
13.248
13.248
Test
Test
Test
Test
13.248
13.248
13.248
13.248
CLK1
35.328
35.328
35.328
42.4
Test
Test
Test
Test
35.328
2.208
24.73
49.46
CLK2
29.4
47.1
40.4
35.328
Test
Test
Test
Test
Off
Off
35.328
35.328
X2
X1
VD D
VIN
VD D
GND
C LK1
C LK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S1
NC
GND
VDD
GND
S0
OE
S2
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
M
1
0
M
1
0
M
1
0
M
1
16 Pin (150 m il) SO IC
0=connect directly to GND
M=leave unconnected (floating)
1=connect directly to VDD
Pin Descriptions
Pin
Number
1
2
3,5,13
4
6,12,14
7
8
9
10
11
15
16
Pin
Name
X2
X1
VDD
VIN
GND
CLK1
CLK2
S2
OE
S0
NC
S1
Pin
Type
Input
Input
Power
Input
Power
Output
Output
Input
Input
Input
-
Input
Pin Description
Crystal connection. Connect to a pullable crystal of 13.248 MHz.
Crystal connection. Connect to a pullable crystal of 13.248 MHz.
Connect to +3.3V.
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO
frequency.
Connect to ground.
Clock output #1 per table above.
Clock output #2 per table above.
Select input #2. Selects outputs per table above. Internal pull-up resistor.
Output enable. Tri-states outputs when low. Internal pull-up resistor.
Select input #0. Selects outputs per table above.
No connect. Do not connect anything to this pin.
Select input #1. Selects outputs per table above.
MDS 3732-07 F
2
Revision 100102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK3732-07
ADSL VCXO C
LOCK
S
OURCE
External Component Selection
The MK3732-07 requires a minimum number of
external components for proper operation.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3732-07 to 3.3V. Connect
pin 4 of the MK3732-07 to the second power supply.
Adjust the voltage on pin 4 to 0V. Measure and record
the frequency of the CLK output.
2. Adjust the voltage on pin 4 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
6
(
f
3.3V
–
f
t arg et
)
+
(
f
0V
–
f
t arg et
)
Error = 10 x -----------------------------------------------------------------------------
–
error
xtal
-
f
t arg et
Decoupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND on pins 3 and 6, on pins 5 and
6, and on pins 13 and 14, as close to the MK3732-07
as possible. For optimum device performance, the
decoupling capacitors should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and
the loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance) place a 33Ω resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
Quartz Crystal
The MK3732-07 VCXO function consists of the
external crystal and the integrated VCXO oscillator
circuit. To assure the best system performance
(frequency pull range) and reliability, a crystal device
with the recommended parameters must be used, and
the layout guidelines discussed in the following section
must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3732-07 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3732-07 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3732-07. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
Please see application note MAN05 for recommended
crystal parameters and suppliers.
Where:
f
target
= nominal crystal frequency
error
xtal
=actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
MDS 3732-07 F
3
Revision 100102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK3732-07
ADSL VCXO C
LOCK
S
OURCE
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3732-07. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5V to VDD+0.5V
-40 to +85°C
-65 to +150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
-40
+3.15
Typ.
–
Max.
+85
+3.45
Units
°C
V
Refer to page 3
DC Electrical Characteristics
VDD=3.3V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Input High Voltage, binary
inputs
Input High Voltage, trinary input
Input Low Voltage, binary
inputs
Symbol
VDD
V
OH
V
OL
V
OH
V
IH
V
IH
V
IL
Conditions
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -8 mA
S2, S1, OE
S0
S2, S1, OE
Min.
3.15
2.4
Typ.
3.3
Max.
3.45
0.4
Units
V
V
V
V
V
V
VDD-0.4
2.0
VDD-0.5
0.8
V
MDS 3732-07 F
4
Revision 100102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK3732-07
ADSL VCXO C
LOCK
S
OURCE
Parameter
Input Low Voltage, trinary input
Operating Supply Current
Short Circuit Current
Input Capacitance
Frequency synthesis error
VIN, VCXO Control Voltage
Symbol
V
IL
IDD
I
OS
Conditions
S0
No load
S2:S0, OE
Both clocks
Min.
Typ.
12
±50
5
Max.
0.5
Units
V
mA
mA
pF
0
0
3.3
ppm
V
V
IA
AC Electrical Characteristics
VDD = 3.3V ±5%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Crystal Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty
Cycle
Maximum Absolute
Jitter
Phase Noise, relative to
carrier
Output pullability, note 1
f
P
Symbol
f
in
t
OR
t
OF
t
D
t
j
Conditions
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
Min.
Typ.
13.248
Max. Units
MHz
1.5
1.5
ns
ns
%
ps
dBc/Hz
ppm
40
±150
60
10 kHz offset
0V < VIN < 3.3V
±100
-115
Note 1: External pullable crystal must conform with those listed in application note MAN05
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 3732-07 F
5
Revision 100102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
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