UC1825A-SP
www.ti.com
.....................................................................................................................................................
SLUS873A – JANUARY 2009 – REVISED APRIL 2009
RAD-TOLERANT CLASS-V, HIGH-SPEED PWM CONTROLLER
1
FEATURES
QML-V Qualified, SMD 5962-87681
Rad-Tolerant: 30 kRad (Si) TID
(1)
Compatible With Voltage-Mode or
Current-Mode Control Methods
Practical Operation at Switching Frequencies
to 1 MHz
50-ns Propagation Delay to Output
High-Current Dual Totem Pole Outputs
(2-A Peak)
Trimmed Oscillator Discharge Current
Low 100-µA Startup Current
Pulse-by-Pulse Current Limiting Comparator
Latched Overcurrent Comparator With Full
Cycle Restart
Radiation tolerance is a typical value based upon initial device
qualification with dose rate = 10 mrad/sec. Radiation Lot
Acceptance Testing is available - contact factory for details.
DESCRIPTION
The UC1825A PWM controller is an improved version
of the standard UC1825 family. Performance
enhancements have been made to several of the
circuit blocks. Error amplifier gain bandwidth product
is 12 MHz, while input offset voltage is 2 mV. Current
limit threshold is assured to a tolerance of 5%.
Oscillator discharge current is specified at 10 mA for
accurate dead time control. Frequency accuracy is
improved to 6%. Startup supply current, typically 100
µA,
is ideal for off-line applications. The output drivers
are redesigned to actively sink current during UVLO
at no expense to the startup current specification. In
addition each output is capable of 2-A peak currents
during transitions.
xxx
•
•
•
•
•
•
•
•
•
•
(1)
xxx
BLOCK DIAGRAM
µ
µ
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
UC1825A-SP
SLUS873A – JANUARY 2009 – REVISED APRIL 2009
.....................................................................................................................................................
www.ti.com
This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Functional improvements have also been implemented in this family. The UC1825 shutdown comparator is now
a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that
ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs
are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to
insure that the fault frequency does not exceed the designed soft start period. The UC1825 CLOCK pin has
become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and
has been buffered for easier interfacing.
The UC1825A has dual alternating outputs and the same pin configuration of the UC1825.
A
version parts have
UVLO thresholds identical to the original UC1825.
ORDERING INFORMATION
(1)
T
A
–55°C to 125°C
(1)
(2)
PACKAGE
(2)
CDIP-16
ORDERABLE PART NUMBER
5962-8768105VEA
TOP-SIDE MARKING
UC1825AJ-SP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at
www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
PIN ASSIGNMENTS
J PACKAGE
(TOP VIEW)
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
THERMAL INFORMATION
PACKAGE
J-16
(1)
θ
JA
80-120
θ
JC
28
(1)
θJC
data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states, "The baseline values shown are worst case (mean
+ 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device die
size greater than 14400 square mils use the following values; dual-in-line, 11°C/W; flat pack, 10°C/W; pin grid array, 10°C/W".
2
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UC1825A-SP
Copyright © 2009, Texas Instruments Incorporated
UC1825A-SP
www.ti.com
.....................................................................................................................................................
SLUS873A – JANUARY 2009 – REVISED APRIL 2009
Terminal Functions
TERMINAL
NAME
CLK/LEB
CT
EAOUT
GND
ILIM
INV
NI
OUTA
OUTB
PGND
RAMP
RT
SS
VC
VCC
VREF
NO.
4
6
3
10
9
1
2
11
14
12
7
5
8
13
15
16
O
I
I
I
I
I
I
O
O
I/O
O
I
O
Output of the internal oscillator
Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be
connected to the device ground using minimal trace length.
Output of the error amplifier for compensation
Analog ground return pin
Input to the current limit comparator
Inverting input to the error amplifier
Non-inverting input to the error amplifier
High current totem pole output A of the on-chip drive stage.
High current totem pole output B of the on-chip drive stage.
Ground return pin for the output driver stage
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation,
this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode
operation, this serves as the slope compensation input.
Timing resistor connection pin for oscillator frequency programming
Soft-start input pin which also doubles as the maximum duty cycle clamp.
Power supply pin for the output stage. This pin should be bypassed with a 0.1-µF monolithic ceramic
low ESL capacitor with minimal trace lengths.
Power supply pin for the device. This pin should be bypassed with a 0.1-µF monolithic ceramic low ESL
capacitor with minimal trace lengths
5.1-V reference. For stability, the reference should be bypassed with a 0.1-µF monolithic ceramic low
ESL capacitor and minimal trace length to the ground plane.
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
VALUE
V
IN
I
O
I
O
Supply voltage,
Source or sink current,DC
Source or sink current, pulse (0.5
µs)
Analog inputs
Power ground
Outputs
I
CLK
I
SS
I
OSC
T
J
T
STG
Clock output current
Soft-start sink current
Oscillator charging current
Storage temperature
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds
(1)
I
O(EA)
Error amplifier output current
VC, VCC
OUTA, OUTB
OUTA, OUTB
INV, NI, RAMP
ILIM, SS
PGND
OUTA, OUTB
CLK/LEB
EAOUT
SS
RT
22
0.5
2.2
–0.3 to 7
–0.3 to 6
±0.2
P
GND
- 0.3 to V
C
+ 0.3
–5
5
20
–5
–55 to 150
–65 to 150
300
UNIT
V
A
A
V
V
V
V
mA
mA
mA
mA
°C
°C
°C
Operating virtual junction temperature range
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2009, Texas Instruments Incorporated
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3
UC1825A-SP
SLUS873A – JANUARY 2009 – REVISED APRIL 2009
.....................................................................................................................................................
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (T
A
= T
J
= –55°C to 125°C), unless otherwise noted.
MIN
V
CC
Supply voltage
Sink/source output current (continuous or time average)
Reference load current
12
0
0
MAX
20
100
10
UNIT
V
mA
mA
ELECTRICAL CHARACTERISTICS
T
A
= –55°C to 125°C, R
T
= 3.65 kΩ, C
T
= 1 nF, V
CC
= 12 V, T
A
= T
J
(unless otherwise noted)
PARAMETER
REFERENCE, V
REF
V
O
Ouput voltage range
Line regulation
Load regulation
Total output variation
Temperature stability
(1)
Output noise voltage
Short circuit current
OSCILLATOR
f
OSC
Initial accuracy
(1)
Total variation
(1)
Voltage stability
Temperature stability
High-level output voltage, clock
Low-level output voltage, clock
Ramp peak
Ramp valley
Ramp valley-to-peak
I
OSC
Oscillator discharge current
Input offset voltage
Input bias current
Input offset current
Open loop gain
CMRR
PSRR
I
O(sink)
I
O(src)
Common mode rejection ratio
Power supply rejection ratio
Output sink current
Output source current
High-level output voltage
Low-level output voltage
Gain bandwidth product
(1)
Slew rate
(1)
(1)
Parameters ensured by design and/or characterization, if not production tested.
1 V < V
O
< 4 V
1.5 V < V
CM
< 5.5 V
12 V < V
CC
< 20 V
V
EAOUT
= 1 V
V
EAOUT
= 4 V
I
EAOUT
= –0.5 mA
I
EAOUT
= –1 mA
f = 200 kHz
60
75
85
1
–0.5
4.5
0
6
5
R
T
= OPEN, V
CT
= 2 V
ERROR AMPLIFIER
2
0.6
0.1
95
95
110
2.5
–1.3
4.7
0.5
12
7
5
1
mA
V
Mhz
V/µs
dB
10
3
1
mV
µA
2.6
0.7
1.55
8.5
T
J
= 25°C
R
T
= 6.6 kΩ, C
T
= 220 pF, T
A
= 25°C
Line, temperature
R
T
= 6.6 kΩ, C
T
= 220 pF
12 V < VCC < 20 V
T
(min)
< T
A
< T
(max)
3.7
±5%
4
0
2.8
1
1.8
10
0.2
3
1.25
2
11
mA
V
375
0.9
350
0.82
400
1
425
1.1
450
1.18
1%
kHz
MHz
kHz
MHz
T
J
= 25°C, I
O
= 1 mA
12 V
≤
VCC
≤
20 V
1 mA
≤
I
O
≤
10 mA
Line, load, temperature
T
(min)
< T
A
< T
(max)
10 Hz < f < 10 kHz
VREF = 0 V
30
5.03
0.2
50
60
90
5.05
5.1
2
5
5.15
15
20
5.17
0.4
V
mV
V
mV/°C
µV
RMS
mA
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
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UC1825A-SP
Copyright © 2009, Texas Instruments Incorporated
UC1825A-SP
www.ti.com
.....................................................................................................................................................
SLUS873A – JANUARY 2009 – REVISED APRIL 2009
ELECTRICAL CHARACTERISTICS (Continued)
T
A
= –55°C to 125°C, R
T
= 3.65 kΩ, C
T
= 1 nF, V
CC
= 12 V, T
A
= T
J
(unless otherwise noted)
PARAMETER
PWM COMPARATOR
I
BIAS
Bias current, RAMP
Minimum duty cycle
Maximum duty cycle
t
LEB
R
LEB
V
ZDC
t
DELAY
I
SS
V
SS
I
DSCH
I
SS
I
BIAS
I
CL
t
d
Leading edge blanking time
Leading edge blanking resistance
Delay-to-output time
(1)
TEST CONDITIIONS
V
RAMP
= 0 V
MIN
TYP MAX
–1
–8
0%
UNIT
µA
85%
R
LEB
= 2 kΩ, C
LEB
= 470 pF
V
CLK/LEB
= 3 V
V
EAOUT
= 5 V to 0 V step
V
SS
= 2.5 V
V
SS
= 2.5 V
0 V
≤
V
ILIM
≤
1.5 V
0.95
1.14
V
ILIM
= 0 V to 2 V step
I
OUT
= 20 mA
I
OUT
= 200 mA
I
OUT
= -20 mA
I
OUT
= -200 mA
C
L
= 1 nF
8.3
0.4
VC = VCC = 8 V
1
1.2
50
0.25
1.2
1.9
2
20
9.2
0.8
100
28
8
4.3
100
300
8.5
1.10
375
10.0
1.25
50
14
5
250
0.3
350
0.5
15
1.05
1.26
80
0.45
2.2
2.9
3
45
9.6
1.25
300
36
ns
V
450
11.5
1.4
120
20
ns
kΩ
V
ns
µA
V
µA
V
µA
V
ns
Zero dc threshold voltage, EAOUT V
RAMP
= 0 V
CURRENT LIMIT / START SEQUENCE / FAULT
Soft-start charge current
Full soft-start threshold voltage
Restart discharge current
Restart threshold voltage
ILIM bias current
Current limit threshold voltage
Overcurrent threshold voltage
Delay-to-output time, ILIM
(1)
OUTPUT
Low-level output saturation
voltage
High-level output saturation
voltage
t
r
, t
f
Rise/fall time
(1)
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage
UVLO hysteresis
SUPPLY CURRENT
I
su
I
CC
(1)
Startup current
Input current
Parameters ensured by design and/or characterization, if not production tested.
µA
mA
V
Copyright © 2009, Texas Instruments Incorporated
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UC1825A-SP
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