®
USBUF01P6
EMI FILTER AND LINE TERMINATION
FOR USB UPSTREAM PORTS
IPAD™
APPLICATIONS
EMI Filter and line termination for USB upstream
ports on:
■
■
USB Hubs
PC peripherals
FEATURES
■
■
■
■
Monolithic device with recommended line
termination for USB upstream ports
Integrated Rt series termination and Ct
bypassing capacitors.
Integrated ESD protection
Small package size
SOT-666IP
(Internal Pad)
FUNCTIONAL DIAGRAM
3.3 V
Rt
D1
Ct
Rp
D4
DESCRIPTION
The USB specification requires upstream ports to
be terminated with pull-up resistors from the D+
and D- lines to Vbus. On the implementation of
USB systems, the radiated and conducted EMI
should be kept within the required levels as stated
by the FCC regulations. In addition to the
requirements
of
termination
and
EMC
compatibility, the computing devices are required
to be tested for ESD susceptibility.
The USBUF01P6 provides the recommended line
termination while implementing a low pass filter to
limit EMI levels and providing ESD protection
which exceeds IEC61000-4-2 level 4 standard.
The device is packaged in a SOT-666 which is the
smallest available lead frame package (45%
smaller than the standard SOT323).
BENEFITS
■
EMI / RFI noise suppression
■
Required line termination for USB upstream
ports
■
ESD protection exceeding IEC61000-4-2 level 4
■
High flexibility in the design of high density
boards
■
Tailored to meet USB 2.0 standard (low speed
and high speed data transmission)
Grd
3.3 V
Rt
D2
Ct
D3
COMPLIES WITH THE FOLLOWING STANDARDS:
■
IEC61000-4-2 level4:
15kV (air discharge)
8kV
(contact discharge)
■
MIL STD 883E-Method 3015-7:
Class 3 C = 100 pF R = 1500
Ω
3 positive strikes and 3 negative strikes (F = 1 Hz)
Order Codes
Part Number
USBUF01P6
Marking
U
May 2004
REV. 2
1/7
USBUF01P6
ABSOLUTE MAXIMUM RATING
(T
amb
= 25°C)
Symbol
V
PP
ESD discharge
Parameter
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
MIL STD 883E - Method 3015-7
Value
± 16
±9
± 25
150
-55 to +150
260
-40 to + 85
Unit
kV
°C
°C
°C
°C
T
j
T
stg
T
L
T
op
Junction temperature
Storage temperature range
Maximum lead temperature for soldering during 10 s at 5mm for case
Operating temperature range
ELECTRICAL CHARACTERISTICS
(T
amb
= 25°C)
Symbol
V
RM
V
BR
V
CL
I
RM
I
PP
αT
V
F
Rd
Parameter
Stand-off voltage
Breakdown voltage
Clamping voltage
Leakage current
Peak pulse current
Voltage temperature coefficient
Slope = 1/Rd
I
I
F
V
CL
V
BR
V
RM
I
RM
V
F
V
Forward voltage drop
Dynamic resistance
I
PP
Symbol
V
BR
I
RM
R
t
R
p
C
t
Test conditions
I
R
= 1 mA
V
RM
= 3.3V per line
Tolerance ± 10%
Tolerance ± 10%
Tolerance ± 20%
Min.
6
Typ.
Max.
10
500
Unit
V
nA
W
kW
pF
33
1.5
47
2/7
®
USBUF01P6
TECHNICAL INFORMATION
Fig. A1:
USB Standard requirements.
3.3V
1.5k
Rt
D+
Twisted pair shielded
D+
Rt
Ct
Rt
Full-speed or
Low-speed USB
Transceiver
Ct
Rt
Full-speed USB
Transceiver
D-
Host or
Hub port
Ct
15k
15k
Zo = 90ohms
5m max
D-
Ct
Hub 0 or
Full-speed function
FULL SPEED CONNECTION
3.3V
1.5k
Rt
D+
Untwisted unshielded
D+
Rt
Ct
Rt
Full-speed or
Low-speed USB
Transceiver
Ct
Rt
Low-speed USB
Transceiver
D-
Host or
Hub port
Ct
15k
15k
3m max
D-
Ct
Hub 0 or
Low-speed function
LOW SPEED CONNECTION
APPLICATION EXAMPLE
Fig. A2:
Implementation of ST' solutions for USB ports.
Downstream port
Host/Hub USB por transceivert
USBDF01W5
Rt
D+ in
Ct Rd
D+ out
USBUF01W6
D2
Gnd
D1
Upstream port
D+
Peripheral transceiver
D+
D+
CABLE
D+
Ct
Rt
Ct
Rt
3.3 V
Rp
Gnd
Gnd
Ct Rd
D- in
Rt
D- out
D-
D-
D-
D3
3.3V
D4
D-
FULL SPEED CONNECTION
Downstream port
Host/Hub USB por transceivert
USBDF01W5
Rt
D+ in
Ct Rd
D+ out
USBUF01W6
D2
Gnd
D1
Upstream port
D+
Peripheral transceiver
D+
D+
CABLE
D+
Ct
Rt
Ct
Rt
3.3 V
Rp
Gnd
Gnd
Ct Rd
D- in
Rt
D- out
D-
D-
D-
D3
3.3V
D4
D-
LOW SPEED CONNECTION
®
3/7
USBUF01P6
EMI FILTERING
Current FCC regulations requires that class B computing devices meet specified maximum levels for both
radiated and conducted EMI.
- Radiated EMI covers the frequency range from 30MHz to 1GHz.
- Conducted EMI covers the 450kHz to 30MHz range.
For the types of devices utilizing the USB, the most difficult test to pass is usually the radiated EMI test.
For this reason the USBUF01P6 device is aiming to minimize radiated EMI.
The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted
EMI because the magnetic field of both conductors cancels each other.
The inside of the PC environment is very noisy and designers must minimize noise coupling from the
different sources. D+ and D- must not be routed near high speed lines (clocks spikes).
Induced common mode noise can be minimized by running pairs of USB signals parallel to each other and
running grounded guard trace on each side of the signal pair from the USB controller to the USBUF device.
If possible, locate the USBUF device physically near the USB connectors. Distance between the USB
controller and the USB connector must be minimized.
The 47pF (C
t
) capacitors are used to bypass high frequency energy to ground and for edge control, and
are placed between the driver chip and the series termination resistors (R
t
). Both C
t
and R
t
should be
placed as close to the driver chip as is practicable.
The USBUF01P6 ensures a filtering protection against ElectroMagnetic and RadioFrequency
Interferences thanks to its low-pass filter structure. This filter is characterized by the following parameters:
- cut-off frequency
- Insertion loss
- high frequency rejection.
Fig. A3:
USBUF01P6 typical attenuation curve.
0.00
dB
-
-2.50
-
-5.00
-
-7.50
TEST BOARD
UUx
Fig. A4:
Measurement configuration.
50Ω
-
-10.00
-
-12.50
-
-15.00
-
-17.50
-
-20.00
-
-22.50
-
-25.00
1.0M
3.0M
10.0M
30.0M
f/Hz
100.0M
300.0M
1.0G
3.0G
Vg
50Ω
ESD PROTECTION
In addition to the requirements of termination and EMC compatibility, computing devices are required to
be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in
Europe. This test requires that a device tolerates ESD events and remains operational without user
intervention.
The USBUF01P6 is particularly optimized to perform ESD protection. ESD protection is based on the use
of device which clamps at:
V
CL
=
V
BR
+
R
d
⋅
I
PP
This protection function is splitted in 2 stages. As shown in
figure A5,
the ESD strikes are clamped by the
first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R
t
.
Such a configuration makes the output voltage very low at the output.
4/7
®
USBUF01P6
Fig. A5:
USBUF01P6 ESD clamping behavior.
Rg
S1
Rt
S2
Rd
V
PP
Vinput
Voutput
Rd
Rload
V
BR
V
BR
Device
to be
protected
ESD Surge
USBUF01P6
Fig. A6:
Measurement board.
ESD
SURGE
15kV
Air
Discharge
TEST BOARD
U
Vin
Vout
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical
dynamical resistance value R
d
. By taking into account these following hypothesis : R
t
>R
d
, R
g
>R
d
and
R
load
>R
d
, it gives these formulas:
R
g
⋅
V
BR
+
R
d
⋅
V
g
Vinput
= ----------------------------------------------
-
R
g
R
t
⋅
V
BR
+
R
d
⋅
Vinput
-
Voutput
= ---------------------------------------------------------
R
t
The results of the calculation done for V
g
=8kV, R
g
=330Ω (IEC61000-4-2 standard), V
BR
=7V (typ.) and
R
d
= 2Ω (typ.) give:
Vinput = 55.48 V
Voutput = 10.36 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due
the low current involved after the resistance R
t
.
The measurements done hereafter show very clearly (fig.
A7)
the high efficiency of the ESD protection :
- no influence of the parasitic inductances on Voutput stage
- Voutput clamping voltage very close to V
BR
(breakdown voltage) in the positive way and -V
F
(forward
voltage) in the negative way
®
5/7
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