CY28419
Clock Synthesizer with Differential SRC and
CPU Outputs
Features
•
•
•
•
•
•
•
CK409B-compliant
Supports Intel Pentium
4-type CPUs
Selectable CPU frequencies
3.3V power supply
Ten copies of PCI clocks
Two copies 48-mHz clock
Five copies of 3V66 with one optional VCH
Four differential CPU clock pairs
One differential SRC clock
I
2
C support with readback capabilities
Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 56-pin SSOP package
CPU
x4
SRC
x1
3V66
x5
PCI
x 10
REF
x2
48M
x2
•
•
•
•
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF0:1
VDD_CPU
CPUT(0:3), CPUC(0:3)
VDD_SRC
SRCT, SRCC
[1]
XTAL
OSC
PLL 1
PLL Ref Freq
Divider
Network
FS_(A:B)
VTT_PWRGD#
IREF
VDD_3V66
3V66_(0:3)
PLL2
2
VDD_PCI
PCIF(0:2)
PCI(0:6)
3V66_4/VCH
PD#
VDD_48MHz
DOT_48
USB_48
SDATA
SCLK
I
2
C
Logic
REF_0
REF_1
VDD_REF
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PCI6
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
3V66_2
3V66_3
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_B
VDD_A
VSS_A
VSS_IREF
IREF
FS_A
CPUT3
CPUC3
VDD_CPU
CPUT2
CPUC2
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
VDD_48
VSS_48
DOT_48
USB_48
SDATA
3V66_4/VCH
SSOP-56
CY28419
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation
Document #: 38-07444 Rev. *D
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 05, 2004
CY28419
Pin Description
Pin No.
1,2
4
Pin Name
REF(0:1)
XIN
Pin Type
O, SE
I
Pin Description
Reference Clock.
3.3V 14.318-Mz clock output.
Crystal Connection or External Reference Frequency Input.
This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection.
Connection for an external 14.318-MHz crystal output.
CPU Clock Output.
Differential CPU clock outputs. See
Table 1
for frequency config-
uration.
CPU Clock Output.
Differential CPU clock outputs. See
Table 1
for frequency config-
uration.
Differential serial reference clock.
66-MHz Clock Output.
3.3V 66-MHz clock from internal VCO.
48-/66-MHz Clock Output.
3.3V selectable through SMBus to be 66 or 48 MHz.
Free Running PCI Output.
33-MHz clocks divided down from 3V66.
PCI Clock Output.
33-MHz clocks divided down from 3V66.
Fixed 48-MHz clock output.
Fixed 48-MHz clock output.
3.3V LVTTL input for CPU frequency selection.
Current Reference.
A precision resistor is attached to this pin which is connected to
the internal current reference.
3.3V LVTTL input for power-down# active LOW.
3.3V LVTTL input is a level-sensitive strobe used to latch the FS0 input
(active
LOW).
SMBus-compatible SDATA.
SMBus-compatible SCLOCK.
Ground for current reference.
3.3V power supply for PLL.
Ground for PLL.
3.3V power supply for outputs.
Ground for outputs.
3.3V power supply for outputs.
Ground for outputs.
3.3V power supply for outputs.
Ground for outputs.
3.3V power supply for outputs.
Ground for outputs.
3.3V power supply for outputs.
Ground for outputs.
3.3V power supply for outputs.
Ground for outputs.
5
41,44,47,50
40,43,46,49
38, 37
22,23,26,27
29
7,8,9
XOUT
CPUT(0:3)
CPUC(0:3)
SRCT, SRCC
3V66(3:0)
3V66_4VCH
PCIF(0:2)
O, SE
O, DIF
O, DIF
O, DIF
O, SE
O, SE
O, SE
O, SE
O, SE
O, SE
I
I
I, PU
I
I/O
I
GND
PWR
GND
PWR
GND
PWR
GND
PWR
GND
PWR
GND
PWR
GND
PWR
GND
12,13,14,15, PCI(0:6)
18,19,20
31,
32
51,56
52
21
35
30
28
53
55
54
42,48
45
36
39
34
33
10,16
11,17
24
25
3
6
USB_48
DOT_48
FS_A, FS_B
IREF
PD#
VTT_PWRGD#
SDATA
SCLK
VSS_IREF
VDD_A
VSS_A
VDD_CPU
VSS_CPU
VDD_SRC
VSS_SRC
VDD_48
VSS_48
VDD_PCI
VSS_PCI
VDD_3V66
VSS_3V66
VDD_REF
VSS_REF
Document #: 38-07444 Rev. *D
Page 2 of 16
CY28419
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A and FS_B input values. For all logic levels
of FS_A and FS_B except MID, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
Table 1. Frequency Select Table (FS_A FS_B)
FS_A
0
0
0
1
1
1
FS_B
0
MID
1
0
1
MID
CPU
100 MHz
REF/N
200 MHz
133 MHz
166 MHz
Hi-Z
SRC
100/200 MHz
REF/N
100/200 MHz
100/200 MHz
100/200 MHz
Hi-Z
3V66
66 MHz
REF/N
66 MHz
66 MHz
66 MHz
Hi-Z
PCIF/PCI
33 MHz
REF/N
33 MHz
33 MHz
33 MHz
Hi-Z
REF0
14.3 MHz
REF/N
14.3 MHz
14.3 MHz
14.3 MHz
Hi-Z
REF1
14.31 MHz
REF/N
14.31 MHz
14.31 MHz
14.31 MHz
Hi-Z
USB/DOT
48 MHz
REF/N
48 MHz
48 MHz
48 MHz
Hi-Z
VTT_PWRGD# has been sampled low, all further
VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In
the case where FS_B is at mid level when VTT_PWRGD# is
sampled low, the clock chip will assume “Test Clock Mode”.
Once “Test Clock Mode” has been invoked, all further FS_B
transitions will be ignored and FS_A will asynchronously
select between the Hi-Z and REF/N mode. Exiting test mode
is accomplished by cycling power with FS_B in a high or low
state.
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A
0
0
1
1
FS_B
0
1
0
1
CPU
200 MHz
400 MHz
266 MHz
333 MHz
SRC
100/200 MHz
100/200 MHz
100/200 MHz
100/200 MHz
3V66
66 MHz
66 MHz
66 MHz
66 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
REF0
14.3 MHz
14.3 MHz
14.3 MHz
14.3 MHz
REF1
14.31 MHz
14.31 MHz
14.31 MHz
14.31 MHz
USB/DOT
48 MHz
48 MHz
48 MHz
48 MHz
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in
Table 3.
The block write and block read protocol is outlined in
Table 4
while
Table 5
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte
read or byte write operation
Byte offset for byte read or byte write operation.
For block read or block write operations, these bits
should be '0000000'
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Description
Block Read Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Description
Document #: 38-07444 Rev. *D
Page 3 of 16
CY28419
Table 4. Block Read and Block Write Protocol
(continued)
Block Write Protocol
19
20:27
28
29:36
37
38:45
46
....
....
....
....
....
....
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
Byte Read Protocol
Description
Block Read Protocol
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Document #: 38-07444 Rev. *D
Page 4 of 16
CY28419
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
0
0
1
1
Externally
Selected
Externally
Selected
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FS_B
FS_A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FS_B reflects the value of the FS_B pin sampled on power-up.
0 = FS_B low at power-up
FS_A reflects the value of the FS_A pin sampled on power-up.
0 = FS_A low at power-up
Description
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
1
1
Name
SRCT, SRCC
SRCT, SRCC
Reserved
Reserved
Reserved
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
Description
Allow control of SRCT/C with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
SRCT/C Output Enable
0 = Disabled (three-state), 1 = Enabled
Reserved
Reserved
Reserved
CPUT/C2 Output Enable
0 = Disabled (three-state), 1 = Enabled
CPUT/C1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
CPUT/C0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
SRCT, SRCC
SRCT, SRCC
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
Reserved
Reserved
Reserved
Description
SRCT/C Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
SRCT/C Stop drive mode
0 = Driven in PCI_STP, 1 = Three-state in power-down
CPUT/C2 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
CPUT/C1 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
CPUT/C0 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
Reserved
Reserved
Reserved
Document #: 38-07444 Rev. *D
Page 5 of 16
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