19-6307; Rev 6/12
DS1314
3V Nonvolatile Controller with Lithium Battery Monitor
FEATURES
Converts CMOS SRAM into nonvolatile
memory
Unconditionally write-protects SRAM when
V
CC
is out of tolerance
Automatically switches to battery backup
supply when V
CC
power failure occurs
Monitors voltage of a lithium cell and
provides advanced warning of impending
battery failure
Signals low-battery condition on active low
Battery Warning output signal
Automatic V
CC
power-fail detection for 3.0V
or 3.3V power supplies
Space-saving 8-pin DIP and SOIC packages
Optional 16-pin SOIC and 20-pin TSSOP
versions reset processor when power failure
occurs and hold processor in reset during
system power-up
Industrial temperature range of -40°C to
+85°C
PIN ASSIGNMENT
V
CCO
V
BAT
TOL
GND
1
2
3
4
8
7
6
5
V
CCI
BW
CEO
CEI
V
CCO
V
BAT
TOL
GND
1
2
3
4
8
7
6
5
V
CCI
BW
CEO
CEI
DS1314 8-Pin DIP
(300 mils)
NC
V
CCO
NC
V
BAT
NC
TOL
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
V
CCI
RST
NC
BW
CEO
NC
CEI
DS1314S-2 8-Pin SOIC
(150 mils)
NC
V
CCO
NC
V
BAT
NC
NC
TOL
NC
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
V
CCI
RST
NC
NC
BW
NC
CEO
NC
CEI
DS1314S 16-Pin SOIC
(300 mils)
DS1314E 20-Pin TSSOP
PIN DESCRIPTION
V
CCI
V
CCO
V
BAT
CEI
CEO
BW
TOL
GND
NC
RST
- Power Supply Input
- SRAM Power Supply Output
- Backup Battery Input
- Chip Enable Input
- Chip Enable Output
- V
CC
Tolerance Select
- Battery Warning Output
(Open Drain)
- Reset Output (Open Drain)
- Ground
- No Connection
DESCRIPTION
The DS1314 Nonvolatile Controller with Battery Monitor is a CMOS circuit which solves the application
problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-
of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write
protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry
uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery
consumption.
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DS1314
In addition to battery-backup support, the DS1314 performs the important function of monitoring the
remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life.
Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority
of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1314
performs such measurement by periodically comparing the voltage of the battery as it supports an internal
resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference
voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning
pin is activated to signal the need for battery replacement.
The DS1314 performs all the circuit functions required to provide battery-backup for an SRAM. First, the
device provides a switch to direct power from the battery or the system power supply (V
CCI
). Whenever
V
CCI
is less than the switch point V
SW
and V
CCI
is less than the battery voltage V
BAT
, the battery is
switched in to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts.
Second, the DS1314 handles power failure detection and SRAM write protection. V
CCI
is constantly
monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and
inhibits chip enable output (
CEO
) in order to write-protect the SRAM. This is accomplished by holding
CEO
to within 0.2 volts of V
CCO
when V
CCI
is out of tolerance. If
CEI
is (active) low at the time that
power failure is detected, the
CEO
signal is kept low until
CEI
is brought high again. Once
CEI
is
brought high,
CEO
is taken high and held high until after V
CCI
has returned to its nominal voltage level. If
CEI
is not brought high by 1.5
µs
after power failure is detected,
CEO
is forced high at that time. This
specific scheme for delaying write protection for up to 1.5
µs
guarantees that any memory access in
progress when power failure occurs will complete properly. Power failure detection occurs at 3.0V
nominal (3.3V supply) when the TOL pin is wired to GND or at 2.7V nominal (3.0V supply) when TOL
is connected to V
CCO
.
MEMORY BACKUP
BATTERY VOLTAGE MONITORING
The DS1314 automatically performs periodic battery voltage monitoring at a factory-programmed time
interval of 24 hours. Such monitoring begins within t
REC
after V
CCI
rises above V
CCTP
, and is suspended
when power failure occurs.
After each 24-hour period (t
BTCN
) has elapsed, the DS1314 connects V
BAT
to an internal 1.2 MΩ test
resistor (R
INT
) for one second (t
BTPW
). During this one second, if V
BAT
falls below the factory-
programmed battery voltage trip point (V
BTP
), the battery warning output
BW
is asserted. While
BW
is
active battery testing will be performed with period t
BTCW
to detect battery removal and replacement.
Once asserted,
BW
remains active until the battery is physically removed and replaced by a fresh cell.
The battery is still re-tested after each V
CC
power-up, however, even if
BW
was active on power-down. If
the battery is found to be higher than V
BTP
during such testing,
BW
is deasserted and regular 24-hour
testing resumes.
BW
has an open-drain output driver.
Battery replacement following
BW
activation is normally done with V
CCI
nominal so that SRAM data is
not lost. During battery replacement, the minimum time duration between old battery detachment and
new battery attachment (t
BDBA
) must be met or
BW
will not deactivate following attachment of the new
2 of 12
DS1314
battery. Should
BW
not deactivate for this reason, the new battery can be detached for t
BDBA
and then re-
attached to clear
BW
.
NOTE:
The DS1314 cannot constantly monitor an attached battery because such monitoring would
drastically reduce the life of the battery. As a result, the DS1314 only tests the battery for one second out
of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that
has not been previously flagged with
BW
) is removed between battery tests, the DS1314 may not
immediately sense the removal and may not activate
BW
until the next scheduled battery test. If a battery
is then reattached to the DS1314, the battery may not be tested until the next scheduled test.
NOTE:
Battery monitoring is only a useful technique when testing can be done regularly over the entire
life of a lithium battery. Because the DS1314 only performs battery monitoring when V
CC
is nominal,
systems which are powered-down for excessively long periods can completely drain their lithium cells
without receiving any advanced warning. To prevent such an occurrence, systems using the DS1314
battery monitoring feature should be powered-up periodically (at least once every few months) in order to
perform battery testing. Furthermore, anytime
BW
is activated on the first battery test after a power-up,
data integrity should be checked via checksum or other technique.
DS1314S and DS1314E varieties have an additional reset pin. These varieties detect out-of-tolerance
power supply conditions and warn a processor-based system of impending power failure. When V
CCI
falls
below the trip point level defined by the TOL pin (V
CCTP
), the V
CCI
comparator activates the reset signal
RST
. Reset occurs at 3.0V nominal (3.3V supply) when the TOL pin is connected to GND or at 2.7V
nominal (3.0V supply) when TOL is connected to V
CCO
.
for 200 ms nominal (t
RPU
). This reset period is sufficiently long to prevent system operation during
power-on transients and to allow t
REC
to expire.
RST
has an open-drain output driver.
When the battery is first attached to the DS1314 without V
CC
power applied, the device does not
immediately provide battery-backup power on V
CCO
. Only after V
CCI
exceeds V
CCTP
and later falls below
both V
SW
and V
BAT
will the DS1314 leave Freshness Seal Mode and provide battery-backup power. This
mode allows a battery to be attached during manufacturing but not used until after the system has been
activated for the first time. As a result, no battery energy is drained during storage and shipping.
RST
also serves as a power-on reset during power-up. After V
CCI
exceeds V
CCTP
,
RST
will be held active
POWER MONITORING
FRESHNESS SEAL MODE
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FUNCTIONAL BLOCK DIAGRAM
Figure 1
DS1314
4 of 12
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
Storage Temperature Range
Soldering Temperature (reflow, SO or TSSOP)
Lead Temperature (soldering, 10s)
ABSOLUTE MAXIMUM RATINGS
DS1314
-0.5V to +6.0V
-40°C to +85°C
-55°C to +125°C
+260°C
+300°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
PDIP
Junction-to-Ambient Thermal Resistance (θ
JA
).…………………...………………………....110°C/W
Junction-to-Case Thermal Resistance (θ
JC
)……………………………………………………40°C/W
8 SO
Junction-to-Ambient Thermal Resistance (θ
JA
).……………………………………………...132°C/W
Junction-to-Case Thermal Resistance (θ
JC
)……………………………………………………38°C/W
16 SO
Junction-to-Ambient Thermal Resistance (θ
JA
).…………………...………………………......71°C/W
Junction-to-Case Thermal Resistance (θ
JC
)……………………………………………………23°C/W
TSSOP
Junction-to-Ambient Thermal Resistance (θ
JA
).……………………………………………..73.8°C/W
Junction-to-Case Thermal Resistance (θ
JC
)……………………………………………………20°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board for the SMT packages. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-
tutorial.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage TOL=GND
Supply Voltage TOL=V
CCO
Battery Supply Voltage
Logic 1 Input
Logic 0 Input
SYMBOL
V
CCI
V
CCI
V
BAT
V
IH
V
IL
MIN
3.0
2.7
2.0
2.0
-0.3
TYP
3.3
3.0
MAX
3.6
3.3
6.0
V
CCI
+0.3
+0.8
(-40°C to +85°C)
UNITS
V
V
V
V
V
NOTES
2
2
2
2, 13
2, 13
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Current (TTL inputs)
Operating Current (CMOS inputs)
RAM Supply Current
(V
CCO
≥
V
CCI
-0.2V)
RAM Supply Current
(V
CCO
≥
V
CCI
-0.3V)
V
CC
Trip Point (TOL=GND)
V
CC
Trip Point (TOL=V
CCO
)
SYMBOL
I
CC1
I
CC2
I
CCO1
I
CCO1
V
CCTP
V
CCTP
MIN
TYP
50
30
(-40°C to +85°C; V
CCI
=
≥V
CCTP
)
MAX
200
100
80
140
UNITS
µA
µA
mA
mA
V
V
NOTES
3
3, 6
4
5
2
2
2.8
2.5
5 of 12
2.9
2.6
3.0
2.7
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