CY28341
Universal Single-Chip Clock Solution for VIA P4M266/KM266
DDR Systems
Features
•
•
•
•
•
Supports VIA P4M266/KM266 chipsets
Supports Pentium® 4, Athlon™ processors
Supports two DDR DIMMS
Supports three SDRAMS DIMMS at 100 MHz
Provides:
— Two different programmable CPU clock pairs
— Six differential SDRAM DDR pairs
— Three low-skew/low-jitter AGP clocks
— Seven low-skew/low-jitter PCI clocks
— One 48M output for USB
•
•
•
•
•
— One programmable 24M or 48M for SIO
Dial-a-Frequency™ and Dial-a-dB features
Spread Spectrum for best electromagnetic interference
(EMI) reduction
Watchdog feature for systems recovery
SMBus-compatible for programmability
56-pin SSOP and TSSOP packages
Table 1. Frequency Selection Table
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1100
1111
CPU
66.80
100.00
120.00
133.33
72.00
105.00
160.00
140.00
77.00
110.00
180.00
150.00
90.00
100.00
200.00
133.33
AGP
66.80
66.80
60.00
66.67
72.00
70.00
64.00
70.00
77.00
73.33
60.00
60.00
60.00
66.67
66.67
66.67
PCI
33.40
33.40
30.00
33.33
36.00
35.00
32.00
35.00
38.50
36.67
30.00
30.00
30.00
33.33
33.33
33.33
Block Diagram
XIN
XOUT
XTAL
REF0
VDDR
REF(0:1)
VDDI
CPUCS_T/C
FS0
Pin Configuration
[1]
*FS0/REF0
VSSR
XIN
XOUT
VDDAGP
AGP0
*SELP4_K7/AGP1
AGP2
VSSAGP
**FS1/PCI_F
**SELSDR_DDR/PCI1
*MULTSEL/PCI2
VSSPCI
PCI3
PCI4
VDDPCI
PCI5
PCI6
VSS48M
**FS3/48M
**FS2/24_48M
VDD48M
VDD
VSS
IREF
*PD#/SRESET#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VTTPWRGD#/REF1
VDDR
VSSC
CPUT/CPUOD_T
CPUC/CPUOD_C
VDDC
VDDI
CPUCS_C
CPUCS_T
VSSI
FBOUT
BUF_IN
DDRT0/SDRAM0
DDRC0/SDRAM1
DDRT1/SDRAM2
DDRC1/SDRAM3
VDDD
VSSD
DDRT2/SDRAM4
DDRC2/SDRAM5
DDRT3/SDRAM6
DDRC3/SDRAM7
VDDD
VSSD
DDRT4/SDRAM8
DDRC4/SDRAM9
DDRT5/SDRAM10
DDRC5/SDRAM11
SELP4_K7#
VDDC
CPU(0:1)/CPU0D_T/C
VDDPCI
FS2
PLL1
FS3 FS1
PCI(3:6)
PCI_F
MULTSEL
PCI2
PCI1
VDDAGP
AGP(0:2)
VDD48M
48M
/2
PD#
SDATA
SCLK
SMBus
PLL2
WDEN
24_48M
WD
SELSDR_DDR
Buf_IN
S2D
CONVERT
SRESET#
VDDD
FBOUT
DDRT(0:5)/SDRAM(0,2,4,6,8,10)
DDRC(0:5)/SDRAM(1,3,5,7,9,11)
56 pin SSOP
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation
Document #: 38-07367 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 26, 2002
C Y 283 41
CY28341
Pin Description
[2]
Pin
3
4
1
XIN
XOUT
FS0/REF0
VDD
VDD
Name
PWR
I/O
I
O
Description
Oscillator Buffer Input.
Connect to a crystal or to an external clock.
Oscillator Buffer Output.
Connect to a crystal. Do not connect when an
external clock is applied at X
IN
.
I/O
Power-on Bidirectional Input/Output.
At power-up, FS0 is the input. When
PU the power supply voltage crosses the input threshold voltage, FS0 state is
latched and this pin becomes REF0, buffered copy of signal applied at XIN.
I
If SELP4_K7 = 1, with a P4 processor setup as CPUT/C. At power-up,
VTT_PWRGD# is an input. When this input transitions to a logic LOW, the FS
(3:0) and MULTSEL are latched and all output clocks are enabled. After the
first HIGH to LOW transition on VTT_PWRGD#, this pin is ignored and will not
effect the behavior of the device thereafter. When the VTT_PWRGD# feature
is not used, please connect this signal to ground through a 10KΩ resistor.
If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin
becomes REF1 and is a buffered copy of the signal applied at X
IN
.
These pins are programmable through strapping pin11, SELSDR_DDR#.If
SELSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They
are “True” copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must
be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase with)
signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V
These pins are programmable through strapping pin11, SELSDR_DDR#.If
SelSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are
“Complementary” copies of signal applied at Pin45, BUF_IN. In this mode,
VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(1,3,5,7,9,11) single-ended clock outputs, copies of (and in phase with)
signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V.
56
VTTPWRGD#
VDDR
REF1
VDDR
O
44,42,38, DDRT
VDDD
36,32,30 (0:5)/SDRAM(0,2,4,6,
8,10)
O
43,41,37 DDRC
VDDD
35,31,29 (0:5)/SDRAM(1,3,5,7,
9,11)
O
7
SELP4_K7 / AGP1
VDDAG
P
I/O
Power-on Bidirectional Input/Output.
At power-up, SELP4_K7 is the input.
PU When the power supply voltage crosses the input threshold voltage, SELP4_K7
state is latched and this pin becomes AGP1 clock output. SELP4_K7 = 1, P4
mode. SELP4_K7 = 0, K7 mode.
I/O
Power-on Bidirectional Input/Output.
At power-up, MULTSEL is the input.
PU When the power supply voltage crosses the input threshold voltage, MULTSEL
state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is
4 x IREFMULTSEL = 1, Ioh is 6 x IREF.
O
3.3V CPU Clock outputs.
This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock
Output. See
Table 1.
3.3V CPU Clock outputs.
This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock
Output. See
Table 1.
2.5V CPU Clock Outputs for Chipset.
See
Table 1.
PCI Clock Outputs.
Are synchronous to CPU clocks. See
Table 1.
12
MULTSEL / PCI2
VDDPCI
53
CPUT/CPUOD_T
VDDC
52
CPUC/CPUOD_C
VDDC
O
48,49
CPUCS_T/C
VDDI
VDDPCI
VDDPCI
O
O
14,15,17, PCI (3:6)
18
10
FS1/PCI_F
I/O
Power-on Bidirectional Input/Output.
At power-up, FS0 is the input. When
PD the power supply voltage crosses the input threshold voltage, FS1 state is
latched and this pin becomes PCI_F clock output.
I/O
Power-on Bidirectional Input/Output.
At power-up, FS3 is the input. When
PD the power supply voltage crosses the input threshold voltage, FS3 state is
latched and this pin becomes 48M, a USB clock output.
20
FS3/48M
VDD48M
Document #: 38-07367 Rev. *A
Page 2 of 21
CY28341
Pin Description
[2]
(continued)
Pin
11
Name
PWR
I/O
Description
SELSDR_DDR#/PCI VDDPCI
1
I/O
Power-on Bidirectional Input/Output.
At power-up, SELSDR_DDR is the
PD input. When the power supply voltage crosses the input threshold voltage,
SELSDR_DDR state is latched and this pin becomes PCI clock
output.SelSDR_DDR#. = 0, DDR Mode. SelSDR_DDR#. = 1, SDR Mode.
I/O
Power-on Bidirectional Input/Output.
At power-up, FS2 is the input. When
PD the power supply voltage crosses the input threshold voltage, FS2 state is
latched and this pin becomes 24_48M, a SIO programmable clock output.
O
O
I
AGP Clock Output.
Is synchronous to CPU clocks. See
Table 1.
AGP Clock Output.
Is synchronous to CPU clocks. See
Table 1.
Current reference programming input for CPU buffers. A precise resistor is
attached to this pin, which is connected to the internal current reference.
21
FS2/24_48M
VDD48M
6
8
25
28
AGP0
AGP2
IREF
SDATA
VDDAG
P
VDDAG
P
I/O
Serial Data Input.
Conforms to the Philips I2C specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
I
Serial Clock Input.
Conforms to the Philips I2C specification.
I/O
Power-down Input/System Reset Control Output.
If Byte6 Bit7 = 0, this pin
PU becomes a SRESET# open drain output, and the internal pulled up is not active.
See system reset description. If Byte6 Bit7 = 1 (default), this pin becomes PD#
input with an internal pull-up. When PD# is asserted LOW, the device enters
power-down mode. See power management function.
If SelSDR_DDR#.= 0, 2.5V CMOS type input to the DDR differential buffers.If
SelSDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer.
If SelSDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the DDRT(0:5) signals.If
SelSDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the SDRAM(0:11) signals
3.3V Power Supply for AGP clocks
3.3V Power Supply for CPUT/C clocks
3.3V Power Supply for PCI clocks
3.3V Power Supply for REF clock
2.5V Power Supply for CPUCS_T/C clocks
3.3V Power Supply for 48M
3.3V Common Power Supply
If SelSDR_DDR#.= 0, 2.5V Power Supply for DDR clocksIf SelSDR_DDR#.=
1, 3.3V Power Supply for SDR clocks.
Ground for AGP clocks
Ground for PCI clocks
Ground for CPUT/C clocks
Ground for DDR clocks
Ground for 48M clock
Ground for ICPUCS_T/C clocks
Common Ground
27
26
SCLK
PD#/SRESET#
45
46
BUF_IN
FBOUT
5
51
16
55
50
22
23
34,40
9
13
54
33,39
19
47
24
VDDAGP
VDDC
VDDPCI
VDDR
VDDI
VDD48M
VDD
VDDD
VSSAGP
VSSPCI
VSSC
VSSD
VSS48M
VSSI
VSS
Note:
2. PU = internal Pull-up. PD = internal Pull-down. Typically = 250 kW (range 200 kW to 500 kW).
Document #: 38-07367 Rev. *A
Page 3 of 21
CY28341
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits
should be “0000000”
Block Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8-bit “00000000” stands for
Block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The Block Write and Block Read protocol is outlined in
Table 3,
while
Table 4
outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Block Read and Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Block Write Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8-bit “00000000” stands for
Block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data Byte N/Slave acknowledge...
Data Byte N – 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Document #: 38-07367 Rev. *A
Page 4 of 21
CY28341
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits “1xxxxxxx” stands for
byte operationbit[6:0] of the command code
represents the offset of the byte to be accessed
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits “1xxxxxxx” stands for
byte operationbit[6:0] of the command code
represents the offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Serial Control Registers
Byte 0: Frequency Select Register
Bit
7
6
5
4
3
@Pup
0
H/W Setting
H/W Setting
H/W Setting
0
21
10
1
Pin#
Name
Reserved
FS2
FS1
FS0
Reserved
For Selecting Frequencies see
Table 1.
For Selecting Frequencies see
Table 1.
For Selecting Frequencies see
Table 1.
If this bit is programmed to “1,” it enables Write to bits (6:4,1) for
selecting the frequency via software (SMBus). If this bit is
programmed to a “0,” it enables only Read of bits (6:4,1), which
reflects the hardware setting of FS(0:3).
11
20
7
SELSDR_DDR Only for reading the hardware setting of the SDRAM interface
mode, status of SELSDR_DDR# strapping.
FS3
SELP4_K7
For Selecting frequencies see
Table 1.
Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
Description
2
1
0
H/W Setting
H/W Setting
H/W Setting
Byte 1: CPU Clocks Register
Bit
7
6
5
4
3
2
1
@Pup
0
1
1
1
1
1
1
48,49
53,52
53,52
Pin#
Name
MODE
SSCG
SST1
SST0
CPUCS_T, CPUCS_C
CPUT/CPUOD_T
CPUC/CPUOD_C
CPUT/C
Description
0 = Down Spread. 1 = Center Spread. See
Table 9.
1 = Enable (default). 0 = Disable
Select spread bandwidth. See
Table 9.
Select spread bandwidth. See
Table 9.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW
state.
1 = output enabled (running). 0 = output disable.
In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW,
CPUT stops in a HIGH state, CPUC stops in a LOW state. In P4 mode, 1 =
when PD# asserted LOW, CPUT and CPUC stop in High-Z.
Only For reading the hardware setting of the Pin11 MULT0 value.
Page 5 of 21
0
1
11
MULT0
Document #: 38-07367 Rev. *A
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