CY28326
FTG for VIA PT880 Serial Chipset
Features
•
•
•
•
•
•
Supports P4
CPUs
3.3V power supply
Ten copies of PCI clocks
One 48 MHz USB clock
Two copies of 25 MHz for SRC/LAN clocks
One 48 MHz/24 MHz programmable SIO clock
• Three differential CPU clock pairs
• SMBus support with Byte Write/Block Read/Write
capabilities
• Spread Spectrum EMI reduction
• Dial-A-Frequency
®
features
• Auto Ratio features
• 48-pin SSOP package
Block Diagram
XIN
XOUT
PLL1
CPU_STP#
IREF
Power
on
Latch
/2
Pin Configuration
[1]
REF[0:2]
CPUT[0:2]
CPUC[0:2]
25MHz[0:1]
AGP[0:2]
FS[A:D]
VTTPWRGD#
PCI_STP#
**FSA/REF0
**FSB/REF1
VDDREF
XIN
XOUT
VSSREF
*FSC/PCIF0
*FSD/PCIF1
*Mode/PCIF2
VDDPCI
VSSPCI
PCI0
PCI1
PCI2
PCI3
PCI4
VDDPCI
VSSPCI
*(PCI_STP#)/Ratio0/PCI5
*(CPU_STP#)/Ratio1/PCI6
48MHz
**24_48_SEL/24_48MHz
VSS48
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
IREF
CPUT2
CPUC2
VSSCPU
CPUT1
CPUC1
VDDCPU
CPUT0
CPUC0
VSSSRC
25MHz1
25MHz0
VDDSRC
*VTT_PWRGD/*PD#
SD
ATA
SCLK
SRESET#
AGP2
VSSAGP
VDDAGP
AGP1/*RatioSel
AGP0
CY2 8 3 2 6
PCI[0:6]
PCI_F[0:2]
PLL2
MODE
PD#
SDATA
SCLK
WD
Logic
I2C
Logic
48MHz
24_48MHz
SRESET
48 Pin SSOP
Note:
1. Pins marked with [*] have internal 150kΩ pull-up resistors. Pins marked with [**] have internal 150kΩ pull-down resistors.
Cypress Semiconductor Corporation
Document #: 38-07616 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 22, 2004
CY28326
Pin Definition
Pin No.
1
Name
**FSA/REF0
PWR
VDDREF
Type
I/O
Description
Power-on Bi-directional Input/Output.
At power-up, FSA is the
input. when VTT_PWRGD transitions to a logic high, FSA state is
latched and this pin becomes REF0, buffered output copy of the
device’s XIN clock. Default Internal pull down.
Power-on Bi-directional Input/Output.
At power-up, FSB is the
input. when VTT_PWRGD transitions to a logic high, FSB state is
latched and this pin becomes REF1, buffered output copy of the
device’s XIN clock. Default Internal pull down.
3.3V Power supply for REF clock output.
Oscillator Buffer Input.
Connect to a crystal or to an external
clock.
Oscillator Buffer Input.
Connect to a crystal. Do not connect
when an external clock is applied at XIN.
Ground for REF clock outputs
Power-on Bi-directional Input/ Output.
At power up, FSC is the
input. When the VTT_PWRGD transitions to a logic high, FSC
state is latched and this pin becomes PCIF0. Default Internal pull
up.
Power-on Bi-directional Input/ Output.
At power up, FSD is the
input. When the VTT_PWRGD transitions to a logic high, FSD
state is latched and this pin becomes PCIF. Default Internal pull
up.
Power-on Bi-directional Input/ Output.
At power up,
MODE/PCIF2 is the input. When the power up, MODE state is
latched and then pin9 becomes PCIF2, PCI clock output for PCI
Device.Default pull-up, See
Table 2
3.3V power supply for PCI clock output.
Ground for PCI clock output.
PCI clock outputs.
Ratio0 Output/PCI5 Output.
At power up when RatioSel (pin 26)
strapping = “High” & MODE (pin 9) strapping=”High”, (PCI_STP#)
Ratio0/PCI5 becomes PCI5 clock output. At power up when
RatioSel (pin 26) strapping = “low” & MODE (pin 9) strapping
=”High”, (PCI_STP#)Ratio0/PCI5 becomes Ratio0 output to
support North bridge over freq strapping function. Once
MODE(pin 9) strapping=”Low”, then (PCI_STP#)Ratio0/PCI5
becomes PCI_STP#, Default = “PCI5” see
Table 2,
Default
Internal pull up.
Ratio1 Output/PCI6 Output.
At power up when RatioSel(pin 26)
strapping = “High” & MODE(pin 9) strapping=”High”, (CPU_STP#)
Ratio1/PCI6 becomes PCI6 clock output. At power up when
RatioSel (pin 26) strapping = “low” & MODE(pin 9) strapping
=”High”, (PCI_STP#)Ratio1/PCI6 becomes Ratio1 output to
support North bridge over freq strapping function. Once
MODE(pin 9) strapping=”Low”, then (PCI_STP#)Ratio1/PCI6
becomes CPU_STP#, Default = “PCI6” see
Table 2,
Default
Internal pull up.
48 MHz Clock Output.
Power-on Bi-directional Input/output.
At power up 24_48_SEL
is the input. When VTT_PWRGD is transited to logic high,
24_48_SEL state is latched and this pin becomes 24/48 MHz
output, Default 24_48_SEL= “0”, 48 MHz output.Default Internal
pull down.
Ground for 48 MHz clock output.
2
**FSB/REF1
VDDREF
I/O
3
4
5
6
7
VDDREF
XIN
XOUT
VSSREF
*FSC/PCIF0
VDDPCI
VDDREF
VDDREF
I
I
O
PWR
I/O
8
*FSD/PCIF1
VDDPCI
I/O
9
*MODE/
PCIF2
VDDPCI
I/O
10,17
11,18
12,13,14,15,16
19
VDDPCI
VSSPCI
PCI[0:4]
*(PCI_STP#) VDDPCI
Ratio0/PCI5
I
I
O
O
20
*(CPU_STP#) VDDPCI
Ratio1/PCI6
O
21
22
48 MHz
VDD48
O
I/O
**24_48_SEL/ VDD48
24_48 MHz
23
VSS48
I
Document #: 38-07616 Rev. *A
Page 2 of 23
CY28326
Pin Definition
(continued)
Pin No.
24
25,29
26
Name
VDD48
AGP0/AGP2
*RatioSEL
/AGP1
VDDAGP
VDDAGP
PWR
Type
I
O
I/O
AGP Clock Output.
Power-on Bi-directional Input/output.
At power up, RatioSel is
the input. when the power supply voltage crosses the input
threshold voltage, RatioSel state is latched and this pin becomes
AGP clock output. Default pull-up.
3.3V power supply for AGP clock output.
Ground for AGP clock output.
System Reset Control Output.
Serial clock input.
Conforms to the Philips I
2
C specification.
Serial clock input.
Conforms to the Philips I
2
C specification of a
Slave Receive/Transmit device. it is an input when receiving data.
It is open drain output when acknowledging or transmitting data.
VTT_PWRGD: 3.3V LVTTL input to determine when FS[D:A],
MODE, RatioSEL and 24_48_SEL inputs are valid and ready to
be sampled.
PD#: Invokes powerdown mode. Default Internal pull up.
Power for 25 MHz clock output. 3.3V Power Supply.
25 MHz Clock Output.
Ground for 25 MHz clock output.
CPU Clock outputs.
Power for CPU clock output.
Ground for CPU clock output.
Current Reference.
A precision resistor is attached to this pin,
which is connected to the internal current reference.
Ground for output.
3.3V Power Supply for output
Description
Power for 48MHz clock output.
27
28
30
31
32
VDDAGP
VSSAGP
SRESET#
SCLK
SDATA
I
I
O
I
I/O
33
*VTT_PWRG
D/PD#
I
34
35,36
37
40
43
46
47
48
VDDSRC
25MHz[0:1]
VSSSRC
VDDCPU
VSSCPU
IREF
VSSA
VDDA
VDDSRC
I
O
I
O
I
I
I
I
I
39,38,42,41,45,44 CPU[T/C][0:2] VDDCPU
Table 1. Frequency Table
FS(D:A)
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Gear
Constant
(Million)
25.00258122
37.50387182
75.00774365
37.50387182
75.00774365
75.00774365
75.00774365
75.00774365
18.75193591
25.00258122
37.50387182
37.50387182
18.75193591
25.00258122
37.50387182
37.50387182
Page 3 of 23
CPU (MHz)
110.0
146.6
220.0
183.3
233.3
266.6
333.3
300.0
100.9
133.9
200.9
166.9
100.0
133.3
200.0
166.6
AGP (MHz)
73.3
73.3
73.3
73.3
66.7
66.7
66.7
66.7
67.3
67.0
67.0
66.8
66.7
66.7
66.7
66.7
PCI (MHz)
36.6
36.6
36.6
36.6
33.3
33.3
33.3
33.3
33.6
33.5
33.5
33.4
33.3
33.3
33.3
33.3
SATA (MHz)
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
VCO (MHz)
660.00
586.68
440.00
733.33
466.67
533.33
666.67
600.00
807.2
803.4
803.6
667.6
800.00
800.00
800.00
666.67
Document #: 38-07616 Rev. *A
CY28326
Table 2. Mode Ratio Setting
Power-up Condition
Mode
0
0
1
1
Table 3. Ratio mapping Table
Power-up Frequency value
CPU
100
133
200
166
AGP
66.6
66.6
66.6
66.6
FS1
0
0
1
1
FS[1:0]
FS0
0
1
0
1
Ratio pin mapping
Pin 20
0
0
1
1
Pin 19
0
1
0
1
RatioSel
x
x
0
1
Pin 19
PCI_STP#
PCI_STP#
Ratio0
PCI5
Pin I/O Setting
Pin 20
CPU_STP#
CPU_STP#
Ratio1
PCI6
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
Table 4. Command Code Definition
Bit
7
0 = Block read or block write operation
1 = Byte read or byte write operation
block write and block read operation from any external I
2
C
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For byte write and byte read opera-
tions, the system controller can access individual indexed
bytes. The offset of the indexed byte is encoded in the
command code, as described in
Table 4.
The block write and
block read protocol is outlined in
Table 5
while
Table 6
outlines
the corresponding byte write and byte read protocol.The slave
receiver address is 11010010 (D2h).
Description
(6:5) Device selection bits. Set = 00
(4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 5. Block Read and Block Write protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Page 4 of 23
Block Read Protocol
Description
Document #: 38-07616 Rev. *A
CY28326
Table 5. Block Read and Block Write protocol
(continued)
46
....
....
....
....
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
38
46:39
47
55:48
56
....
....
....
...
Table 6. Byte Read and Byte Write protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Byte Configuration Map
Byte 0: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
HW
HW
HW
HW
0
1
1
1
Name/Pin Affected
FSD
FSC
FSB
FSA
Test bit
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Don’t change, Default =0
CPU[T/C]2 Output Enable
0 = Disabled (tri-sate), 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disabled (tri-sate), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disabled (tri-sate), 1 = Enabled
Description
HW Frequency selection bits [3:0]. See table 2.
Power up latched value
Document #: 38-07616 Rev. *A
Page 5 of 23
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
