CY28323B
FTG for Intel
®
Pentium
®
4 CPU and Chipsets
Features
• Compatible to Intel
®
CK-Titan & CK-408 Clock Synthe-
sizer/Driver Specifications
• System frequency synthesizer for Intel Brookdale 845
and Brookdale - G Pentium
®
4 Chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog timer for system recov-
ery
• Automatically switch to HW selected or SW pro-
grammed clock frequency when Watchdog timer times
out
• Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength support
• Programmable output skew support
• Power management control inputs
• Available in 48-pin SSOP
CPU
x3
3V66
x4
PCI
x 10
REF
x2
48M
x1
24_48M
x1
Block Diagram
X1
X2
Pin Configuration
PLL Ref Freq
Divider
Network
VDD_REF
REF0:1
[1]
XTAL
OSC
PLL 1
VDD_CPU
CPU0:1, CPU0:1#,
CPU_ITP, CPU_ITP#
*FS0:4
VTT_PWRGD#
*MULTSEL0:1
VDD_3V66
3V66_0:3
PWR_DWN#
VDD_PCI
PCI_F0:2
PCI0:6
PLL2
VDD_48MHz
48MHz
24_48MHz
2
SDATA
SCLK
SMBus
Logic
*MULTSEL1/REF1
VDD_REF
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
*FS4/PCI0
PCI1
PCI2
GND_PCI
PCI3
PCI4
PCI5
PCI6
VDD_PCI
VTT_PWRGD#
RST#
GND_48MHz
*FS0/48MHz
*FS1/24_48MHz
VDD_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/MULTSEL0*
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWR_DWN#
CPU0
CPU0#
VDD_CPU
CPU1
CPU1#
GND_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3
SCLK
SDATA
~
CY28323B
RST#
SSOP-48
Note:
1. Signals marked with ‘*’ and “^” have internal pull-up and pull-down resistors respectively.
Cypress Semiconductor Corporation
Document #: 38-07453 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised November 19, 2003
CY28323B
Pin Definitions
Pin Name
X1
Pin No.
3
Pin
Type
I
Pin Description
Crystal Connection or External Reference Frequency Input:
This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection:
Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
Reference Clock 0/Current Multiplier Selection 0:
3.3V 14.318-MHz clock out-
put. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
Reference Clock 1/Current Multiplier Selection 1:
3.3V 14.318-MHz clock out-
put. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
CPU Clock Outputs:
Frequency is set by the FS0:4 inputs or through serial input
interface.
CPU Clock Output for ITP:
Frequency is set by the FS0:4 inputs or through
serial input interface.
66-MHz Clock Outputs:
3.3V fixed 66-MHz clock.
Free-running PCI Output 0/Frequency Select 2:
3.3V free-running PCI output.
This pin also serves as a power-on strap option to determine device operating
frequency as described in the Frequency Selection Table.
Free-running PCI Output 1/Frequency Select 3:
3.3V free-running PCI output.
This pin also serves as a power-on strap option to determine device operating
frequency as described in
Table 4.
Free-running PCI Output 2:
3.3V free-running PCI output.
PCI Output 0/Frequency Select 4:
3.3V PCI output. This pin also serves as a
power-on strap option to determine device operating frequency as described in
Table 4.
PCI Clock Output 1 to 6:
3.3V PCI clock outputs.
48-MHz Output/Frequency Select 0:
3.3V fixed 48-MHz, non-spread spectrum
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 4.
This output will be used as the reference clock for USB host controller in Intel 845
(Brookdale) platforms. For Intel Brookdale - G platforms, this output will be used
as the VCH reference clock.
X2
REF0/MULTSEL0
4
48
O
I/O
REF1/MULTSEL1
1
I/O
CPU0:1, CPU0:1#
CPU_ITP,
CPU_ITP#
3V66_0:3
PCI_F0/FS2
41, 38, 40,
37
44, 45
31, 30, 28,
27
6
O
I/O
O
I/O
PCI_F1/FS3
7
I/O
PCI_F2
PCI0/FS4
8
10
I/O
I/O
PCI1:6
48MHz/FS0
11, 12, 14,
15, 16, 17
22
O
I/O
Document #: 38-07453 Rev. *B
Page 2 of 22
CY28323B
Pin Definitions
(continued)
Pin Name
24_48MHz/FS1
Pin No.
23
Pin
Type
I/O
Pin Description
24- or 48-MHz Output/Frequency Select 1:
3.3V fixed 24-MHz or 48-MHz
non-spread spectrum output. This pin also serves as a power-on strap option to
determine device operating frequency as described in
Table 4.
This output will be used as the reference clock for SIO devices in Intel 845
(Brookdale) platforms. For Intel Brookdale - G platforms, this output will be used
as the reference clock for both USB host controller and SIO devices. We recom-
mend system designer to configure this output as 48 MHz and “HIGH Drive” by
setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively.
Power Down Control:
3.3V LVTTL-compatible input that places the device in
power-down mode when held LOW.
SMBus Clock Input:
Clock pin for serial interface.
SMBus Data Input:
Data pin for serial interface.
System Reset Output:
Open-drain system reset output.
PWR_DWN#
SCLK
SDATA
RST#
42
26
25
20
I
I
I/O
O
(open-
drain)
I
I
IREF
VTT_PWRGD#
35
19
Current Reference for CPU Output:
A precision resistor is attached to this pin
which is connected to the internal current reference.
Powergood from Voltage Regulator Module (VRM):
3.3V LVTTL input.
VTT_PWRGD# is a level-sensitive strobe used to determine when FS0:4 and
MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
3.3V Power Connection:
Power supply for CPU outputs buffers, 3V66 output
buffers, PCI output buffers, reference output buffers and 48-MHz output buffers.
Connect to 3.3V.
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
VDD_CORE
GND_CORE
2, 9, 18, 24,
32, 39, 46
P
5, 13, 21, 29,
36, 43, 47
G
Ground Connection:
Connect all ground pins to the common system ground
plane.
34
33
P
G
3.3V Analog Power Connection:
Power supply for core logic, PLL circuitry.
Connect to 3.3V.
Analog Ground Connection:
Ground for core logic, PLL circuitry.
Document #: 38-07453 Rev. *B
Page 3 of 22
CY28323B
Swing Select Functions
MULTSEL1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MULTSEL0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
Reference R, IREF =
VDD/(3*Rr)
Output
Current
I
OH
= 4*Iref
I
OH
= 4*Iref
I
OH
= 5*Iref
I
OH
= 5*Iref
I
OH
= 6*Iref
I
OH
= 6*Iref
I
OH
= 7*Iref
I
OH
= 7*Iref
I
OH
= 4*Iref
I
OH
= 4*Iref
I
OH
= 5*Iref
I
OH
= 5*Iref
I
OH
= 6*Iref
I
OH
= 6*Iref
I
OH
= 7*Iref
I
OH
= 7*Iref
V
OH
@ Z
1.0V @ 50
1.2V @ 60
1.25V @ 50
1.5V @ 60
1.5V @ 50
1.8V @ 60
1.75V @ 50
2.1V @ 60
0.47V @ 50
0.56V @ 60
0.58V @ 50
0.7V @ 60
0.7V @ 50
0.84V @ 60
0.81V @ 50
0.97V @ 60
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Document #: 38-07453 Rev. *B
Page 4 of 22
CY28323B
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or dis-
abled.
The register associated with the Serial Data Interface initializ-
es to its default setting upon power-up, and therefore use of
this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write and block read operation from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individual indexed bytes. The offset
of the indexed byte is encoded in the command code, as de-
scribed in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol.
The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
7
6:0
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these
bits should be ‘0000000’.
Descriptions
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
Document #: 38-07453 Rev. *B
Page 5 of 22
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