UM10601
LPC81x User manual
Rev. 1.6 — 2 April 2014
User manual
Document information
Info
Keywords
Content
ARM Cortex M0+, LPC800, LPC800 UM, LPC81x, LPC81x UM, USART,
I2C, LPC811M001JDH16, LPC812M101JDH16, LPC812M101JD20,
LPC812M101JDH20, LPC810M021FN8, LPC812M101JTB16
LPC81x user manual
Abstract
NXP Semiconductors
UM10601
LPC81x User manual
Revision history
Rev
1.6
Date
20140402
Description
LPC81x user manual
PDF output size corrected.
1.5
Modifications:
20140306
LPC81x user manual
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Table 147 “SCT configuration example”
corrected.
Figure 43 “Boot ROM structure”
corrected.
LPC81x user manual
1.4
Modifications:
20140207
Editorial updates in the SPI chapter. Bit FLEN renamed to LEN in the TXDATCTL and TXCTL registers.
Bit description of the FRAME_DELAY bit in the SPI DELAY register updated. See Table 205.
Chapter 29 “LPC81x Code examples” added.
SCT behavior in undefined state described in Section 10.7.5.
Clarify write access to the following registers in the SCT: COUNT, STATE, MATCH, FRACMAT, and
OUTPUT. Writes are only allowed when the counter is halted.
Clarify repeated access to SCT CTRL register.
Reset value of the SYSAHBCLKCTRL register corrected. See Table 30.
Part LPC812M101JTB16 added.
Code examples corrected in Chapter 23 “LPC81x Power profile API ROM driver”, Chapter 25 “LPC81x
USART API ROM driver routines”, and Chapter 24 “LPC81x I2C-bus ROM API” to comply with
LPCOpen code.
Remark about 5 V tolerance added for digital pins with configurable open-drain mode. See
Section 6.4.4.
Description of the EVn_STATE register clarified. See Table 142 “SCT event state mask registers 0 to 5
(EV[0:5]_STATE, addresses 0x5000 4300 (EV0_STATE) to 0x5000 4328 (EV5_STATE)) bit
description”.
Description of SLEEPFLAG bit corrected in the PCON register. Reading a 1 indicates that the part was
in sleep, deep-sleep, or power-down mode before wake-up. See Table 55 “Register overview: PMU
(base address 0x4002 0000)”.
Added recommendation to use a software delay after power-up of the system oscillator. See
Section 4.6.32 “Power configuration register”.
Section 4.7.1 “Reset”, Section 4.7.2 “Start-up behavior”, Section 4.7.3 “Brown-out detection” added for
clarity.
Description of Go command clarified. See Section 22.5.1.8 “Go <address> <mode>”.
Description of the ARM STIR register removed. This register is not implemented in the ARMv6-M
architecture.
Name “SCT” changed to “SCTimer/PWM” for clarity where appropriate throughout the document.
Behavior of data stalls for different settings of the SPI TXDATCTL register bit EOT clarified.
Section 17.6.7 “SPI Transmitter Data and Control register”.
Add clock frequency parameter to IAP commands “Copy RAM to flash”, “Erase page”, and “Erase
sector”. Table 258, Table 259, Table 266. This parameter has been removed in error in v. 1.3.
Description of MRT one-shot bus stall mode added. See Section 11.5.3 “One-shot bus stall mode” and
Table 151 “Control register (CTRL[0:3], address 0x4000 4008 (CTRL0) to 0x4000 4038 (CTRL3)) bit
description”.
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
User manual
Rev. 1.6 — 2 April 2014
2 of 370
NXP Semiconductors
UM10601
LPC81x User manual
Revision history
…continued
Rev
1.3
Modifications:
Date
20130722
Description
LPC800 user manual
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More explanation added to the SPI Transmitter data and control register. See Table 211.
Changed the ISP entry pin from PIO0_1 to PIO0_12 for TSSOP and SOP packages. See Table 234
“LPC800 flash and ISP configurations” and Table 232 “Pin location in ISP mode”.
Requirement added for entering low power modes: switch the main clock source to IRC before entering
Deep-sleep and Power-down modes. See Section 5.5, Section 5.7.5.2, and Section 5.7.6.2.
Section 3.4 added.
Type numbers updated throughout the document to reflect new operating temperature range. See
Table 1 “Ordering information” and Table 2 “Ordering options”.
Boot Rom revision updated. See Table 231 “Boot loader versions”.
Description of boot loader updated. See Section 21.5.1.
ADDRDET bit description corrected in Table 175 “USART Control register (CTL, address 0x4006 4004
(USART0), 0x4006 8004 (USART1), 0x4006 C004 (USART2)) bit description”. 0 = disabled, 1 =
enabled.
Remove clock frequency parameter from IAP commands “Copy RAM to flash”, “Erase page”, and
“Erase sector”. See Section 22.5.2 “IAP commands”.
IDLE bit renamed to MSTIDLE in Section 17.6.3 “SPI Status register”.
Update IAP description. See Section 22.5.2 “IAP commands”.
Editorial updates. Some register and bit names corrected.
LPC800 user manual
1.2
Modifications:
20130314
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Editorial updates.
Table 53 “PLL configuration examples” updated.
Register bit description of Table 105 “Pattern match bit-slice source register (PMSRC, address 0xA000
402C) bit description” updated.
Chapter 5 “LPC800 Reduced power modes and Power Management Unit (PMU)” updated.
Section 5.3.1 “Low power modes in the ARM Cortex-M0+ core” added.
Removed dependency on system frequency for flash access times in Table 227 “Flash configuration
register (FLASHCFG, address 0x4004 0010) bit description”.
Instructions on how to prevent floating internal pins added. See Section 6.3.
Figure 31 “I2C clocking” updated.
Description of the NMISRC register updated. See Section 4.6.26 “NMI source selection register”.
Section 16.3.1 “I2C transmit/receive in master mode” added.
Chapter 14 “LPC800 ARM Cortex SysTick Timer (SysTick)” added.
Address offset of the DEVICE_ID register corrected. See Table 51 “Device ID register (DEVICE_ID,
address 0x4004 83F8) bit description”.
BOD reset level 0 changed to reserved in Table 41 “BOD control register (BODCTRL, address 0x4004
8150) bit description”.
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
User manual
Rev. 1.6 — 2 April 2014
3 of 370
NXP Semiconductors
UM10601
LPC81x User manual
Revision history
…continued
Rev
1.1
Modifications:
Date
20130124
Description
LPC800 user manual
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Flash signature creation algorithm corrected. See Section 19.5.1 “Flash signature generation”.
System PLL output frequency restricted to < 100 MHz.
MTB register memory space changed to 1 kB in Figure 2 “LPC800 Memory mapping”.
Description of the External trace buffer command register updated. See Section 4.6.20 “External trace
buffer command register”.
Flash interrupt removed in Table 3.
Chapter 27 summarizing the ARM Cortex-M0+ instruction set added.
ISP Read CRC checksum command added. See Section 21.5.1.15 “Read CRC checksum <address>
<no of bytes>”.
Section 20.3.1 “Boot loader versions” added.
MRT implementation changed to 31-bit timer. See Chapter 11. Bit description of Table 140 “Idle
channel register (IDLE_CH, address 0x4000 40F4) bit description” corrected.
Updates for clarification in Chapter 17 “LPC800 SPI0/1”.
Updates for clarification in Chapter 16 “LPC800 I2C-bus interface”.
Updates for clarification in Chapter 15 “LPC800 USART0/1/2”.
Updates for clarification in Chapter 8 “LPC800 Pin interrupts/pattern match engine”.
Updates for clarification in Section 9.4 (switch matrix-to-pin functional diagram).
Updates for clarification in Chapter 5 “LPC800 Reduced power modes and Power Management Unit
(PMU)”.
Section 3.3.2 “Non-Maskable Interrupt (NMI)” and Section 3.3.3 “Vector table offset” added.
Bit fields corrected in Section 10.6.
USART baudrate clock output removed from USART features.
Preliminary LPC800 user manual
1
20121109
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
User manual
Rev. 1.6 — 2 April 2014
4 of 370
UM10601
Chapter 1: LPC81x Introductory information
Rev. 1.6 — 2 April 2014
User manual
1.1 Introduction
The LPC81x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC81x support up to 16 kB of flash memory and
4 kB of SRAM.
The peripheral complement of the LPC81x includes a CRC engine, one I
2
C-bus interface,
up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and
state-configurable timer, one comparator, function-configurable I/O ports through a switch
matrix, an input pattern match engine, and up to 18 general-purpose I/O pins.
For additional documentation related to this part see
Section 30.2 “References”.
1.2 Features
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System:
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ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with
single-cycle multiplier and fast single-cycle I/O port.
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ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
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System tick timer.
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Serial Wire Debug (SWD) and JTAG boundary scan modes (BSDL) supported.
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Micro Trace Buffer (MTB) supported.
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Memory:
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Up to 16 kB on-chip flash programming memory with 64 Byte page write and
erase.
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4 kB SRAM.
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ROM API support:
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Boot loader.
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USART drivers.
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I2C drivers.
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Power profiles.
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Flash In-Application Programming (IAP) and In-System Programming (ISP).
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Digital peripherals:
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High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to
18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and glitch filter.
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High-current source output driver (20 mA) on four pins.
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High-current sink driver (20 mA) on two true open-drain pins.
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GPIO interrupt generation capability with boolean pattern-matching feature on
eight GPIO inputs.
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Switch matrix for flexible configuration of each I/O pin function.
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
User manual
Rev. 1.6 — 2 April 2014
5 of 370
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