PD - 96906C
IRFB4610
IRFS4610
IRFSL4610
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
HEXFET
®
Power MOSFET
D
G
S
V
DSS
R
DS(on)
typ.
max.
I
D
100V
11m
:
14m
:
73A
GDS
TO-220AB
IRFB4610
GDS
D
2
Pak
IRFS4610
GDS
TO-262
IRFSL4610
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dV/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Max.
73
52
290
190
1.3
± 20
7.6
-55 to + 175
300
10lb in (1.1N m)
Units
A
f
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
W
W/°C
V
V/ns
°C
e
x
x
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Ã
d
370
See Fig. 14, 15, 16a, 16b,
mJ
A
mJ
Repetitive Avalanche Energy
f
Thermal Resistance
Symbol
R
θJC
R
θCS
R
θJA
R
θJA
Junction-to-Case
j
Parameter
Typ.
–––
0.50
–––
–––
Max.
0.77
–––
62
40
Units
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
j
Junction-to-Ambient (PCB Mount) , D
2
Pak
ij
www.irf.com
1
01/23/06
IRFB4610/IRFS4610/IRFSL4610
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
–––
11
–––
–––
–––
–––
–––
1.5
–––
14
4.0
20
250
200
-200
–––
Ω
nA
V
0.085 –––
Conditions
V
GS
= 0V, I
D
= 250µA
∆V
(BR)DSS
/∆T
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
Static Drain-to-Source On-Resistance
V
GS(th)
I
DSS
I
GSS
R
G
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
V/°C Reference to 25°C, I
D
= 1mA
mΩ V
GS
= 10V, I
D
= 44A
V
µA
f
V
DS
= V
GS
, I
D
= 100µA
V
DS
= 100V, V
GS
= 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
V
GS
= -20V
f = 1MHz, open drain
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
73
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
90
20
36
18
87
53
70
3550
260
150
330
380
–––
140
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
pF
ns
S
nC
I
D
= 44A
V
DS
= 80V
V
GS
= 10V
V
DD
= 65V
I
D
= 44A
R
G
= 5.6Ω
V
GS
= 10V
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
Conditions
V
DS
= 50V, I
D
= 44A
f
f
h
, See Fig.11
= 0V to 80V
g
, See Fig. 5
Conditions
D
C
oss
eff. (ER) Effective Output Capacitance (Energy Related) –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related)
–––
V
GS
= 0V, V
DS
= 0V to 80V
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
35
42
44
65
2.1
73
290
1.3
53
63
66
98
–––
A
nC
V
ns
A
MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 44A, V
GS
= 0V
T
J
= 25°C
V
R
= 85V,
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
G
Ã
S
f
f
I
F
= 44A
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.39mH
R
G
= 25Ω, I
AS
= 44A, V
GS
=10V. Part not recommended for use
above this value.
I
SD
≤
44A, di/dt
≤
660A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C
2
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IRFB4610/IRFS4610/IRFSL4610
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
10
4.5V
4.5V
≤
60µs PULSE WIDTH
Tj = 25°C
10
0.1
1
10
100
≤
60µs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000.0
Fig 2.
Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current
(Α)
ID = 73A
VGS = 10V
2.5
100.0
TJ = 175°C
10.0
2.0
1.5
1.0
TJ = 25°C
VDS = 25V
1.0
≤
60µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.5
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
6000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
4000
Fig 4.
Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 44A
VDS = 80V
VDS= 50V
VDS= 20V
5000
16
C, Capacitance (pF)
Ciss
12
3000
8
2000
4
1000
Coss
Crss
1
10
100
0
0
0
20
40
60
80
100
120
140
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4610/IRFS4610/IRFSL4610
1000.0
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
100.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
TJ = 175°C
100
10.0
10
1msec
10msec
TJ = 25°C
1.0
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
VGS = 0V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
DC
100
1000
VSD, Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
80
Fig 8.
Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage
125
120
ID , Drain Current (A)
60
115
40
110
20
105
0
25
50
75
100
125
150
175
100
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
TJ , Junction Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
2.0
Fig 10.
Drain-to-Source Breakdown Voltage
1600
1.5
1200
I D
TOP
4.6A
6.3A
BOTTOM
44A
Energy (µJ)
1.0
800
0.5
400
0.0
0
20
40
60
80
100
0
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB4610/IRFS4610/IRFSL4610
1
D = 0.50
Thermal Response ( ZthJC )
0.1
0.20
0.10
0.05
0.02
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
τ
C
τ
1
τ
2
τ
0.01
0.01
τ
J
Ri (°C/W)
τi
(sec)
0.4367 0.001016
0.3337
0.009383
Ci=
τi/Ri
Ci= i/Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
0.0001
1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
0.01
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj
= 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
400
EAR , Avalanche Energy (mJ)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 44A
300
200
100
0
25
50
75
100
125
150
175
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither T
jmax
nor
Iav (max) is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting TJ , Junction Temperature (°C)
Fig 15.
Maximum Avalanche Energy vs. Temperature
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