GDC21D401B
(Video Decoder)
Version 1.0
Mar, 99
HDS-GDC21D401B-9908 / 10
GDC21D401B
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by Hyundai for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Hyundai or others.
These Hyundai products are intended for usage in general electronic equipment (office equipment,
communication equipment, measuring equipment, domestic electrification, etc.).
Please make sure that you consult with us before you use these Hyundai products in equipment which
require high quality and / or reliability, and in equipment which could have major impact to the welfare
of human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these
Hyundai products were used in the mentioned equipment without prior consultation with Hyundai.
Copyright 1999 Hyundai Micro Electronics Co.,Ltd.
All Rights Reserved
3
GDC21D401B
TABLE OF CONTENTS
1. General Description ............................................................................................................5
2. Features...............................................................................................................................5
3. Pin Description....................................................................................................................6
4. Block Diagram ...................................................................................................................10
5. Functional Description .....................................................................................................11
5.1 Initialization and Decoding Start ...................................................................................11
5.2 Picture Decoding ..........................................................................................................11
5.3 STC (System Time Clock) Generation..........................................................................12
5.4 DTS (Decoding Time Stamp) Synchronization..............................................................12
5.5 Error Concealment .......................................................................................................12
5.6 User Data Read............................................................................................................12
5.7 Bitstream Buffer Over/Underflow..................................................................................13
5.8 VLD (Variable Length Decoder) ....................................................................................13
5.9 Inverse Quantization ....................................................................................................13
5.10 IDCT (Inverse Discrete Cosine Transform) .................................................................13
5.11 MC(Motion Compensation) .........................................................................................13
5.12 Transport Interface .....................................................................................................14
5.13 Host Interface.............................................................................................................15
5.14 Video Data Output Format..........................................................................................20
5.15 Video Data Output Timing ..........................................................................................21
5.16 SDRAM Interface .......................................................................................................22
6. Electrical Specification .....................................................................................................24
6.1 Absolute Maximum Rating............................................................................................24
6.2 Recommended Operating Range .................................................................................24
6.3 DC Characteristics (VDD = 3.3 V±10%, TA = 0 ~ 70¡
É
................................................24
)
6.4 AC Characteristics (VDD = 3.3 V±10%, TA = 0 ~ 70¡
É
................................................25
)
7. Package Mechanical Data .................................................................................................26
7.1 Package Pin Out ..........................................................................................................26
7.2 Physical Dimension ......................................................................................................29
4
GDC21D401B
Video Decoder
GDC21D401B
1. General Description
The Video Decoder(VD) decodes video
elementary stream of MPEG-2(ISO/ICE
13818-2)MP@HL. It supports the ATSC
digital TV video standard, and can be used for
the video part of the ATSC digital TV with the
Transport Decoder and the VDP(Video
Display Processor). Picture decoding timing
can be controlled internally for A/V lip
synchronization, and externally for Video
Trick Mode by host microprocessor via I
2
C bus.
The Video Decoder can extract video user data
including caption from video elementary
stream, and host microprocessor can read the
video user data from the Video Decoder(VD)
via I
2
C. It uses four 16x1M SDRAMs and can
support up to 81 MHz memory clock speed.
2. Features
•
Supports MPEG-2 (ISO/ICE 13818-2)
MP@HL
•
Supports all video input formats of ATSC
digital TV standard
•
Supports picture decoding capability up to
1920x1088 30 Frame/Sec
•
Supports all kinds of motion compensation
methods of MPEG-2
•
Supports MPEG-2 error code, syntax error
detection, and slice-based error concealment
•
Supports DTS synchronization
•
Supports VBV delay mode and low delay
mode decoding
•
Supports film mode decoding (3:2 Pull
down)
•
Supports high level commands for trick
mode
•
Supports 8(w)x64(d) internal user data FIFO
•
Outputs: macroblock format
4-pel parallel output
54 MHz synchronous I/F
Data window (pdwin, sclk, and mbclk)
Picture information (Picture structure, Field
parity, and DCT type)
•
External memory for VBV buffer , DTS
FIFO and 2-frame memory:
64-bit Data Bus
81 MHz Synchronous Interface
64-Mbyte
Four 16x1M SDRAMs
•
Host processor interface: I
2
C bus interface
Two interrupt signals
Supports 23 programmable internal
registers
5
GDC21D401B
3. Pin Description
P_SHARE_IN[10]
P_SHARE_IN[9]
P_SHARE_IN[8]
MCLK_OUT
TEST_ OUT[2]
FP_FD
MCLK_IN
DEC_ERROR
VSS
P_WAIT
PIC_DIS_SYNC
VDD
VDD
PDATA[31]
PDATA[30]
PDATA[29]
PDATA[28]
VSS
VSS
PDATA[27]
PDATA[26]
PDATA[25]
PDATA[24]
VDD
PDATA[23]
PDATA[22]
PDATA[21]
PDATA[20]
VSS
PDATA[19]
PDATA[18]
VDD
PDATA[17]
PDATA[16]
PDATA[15]
VDD
PDATA[14]
PDATA[13]
PDATA[12]
VSS
PDATA[11]
VSS
PDATA[10]
VDD
PDATA[9]
PDATA[8]
VDD
PDATA[7]
PDATA[6]
PDATA[5]
PDATA[4]
VSS
VSS
PDATA[3]
VDD
VDD
PDATA[2]
PDATA[1]
PDATA[0]
VSS
235
230
225
220
215
210
205
200
195
190
VSS
SCANTESTON
VDD
IDCTTESTON
MEMTESTON
CLK_27M
VSS
\RESET
TSW
\VIDEN
VSTCW
VSS
VID_STRB
VID_DATA[0]
VID_DATA[1]
VID_DATA[2]
VDD
VID_DATA[3]
VSS
VID_DATA[4]
VID_DATA[5]
VDD
VID_DATA[6]
VSS
VID_DATA[7]
SCL
VSS
SDA
\VID_REQ
\UBUFF_FULL
\INT_V
VDD
SDRAM_DATA[0]
SDRAM_DATA[1]
VSS
SDRAM_DATA[2]
VDD
SDRAM_DATA[3]
SDRAM_DATA[4]
SDRAM_DATA[5]
VDD
SDRAM_DATA[6]
SDRAM_DATA[7]
VDD
SDRAM_DATA[8]
VSS
SDRAM_DATA[9]
SDRAM_DATA[10]
VDD
SDRAM_DATA[11]
SDRAM_DATA[12]
VSS
SDRAM_DATA[13]
SDRAM_DATA[14]
VDD
SDRAM_DATA[15]
SDRAM_DATA[16]
VSS
SDRAM_DATA[17]
SDRAM_DATA[18]
185
1 240
5
180
175
10
170
15
165
20
160
25
HME
GDC21D401B
YYW W A
155
30
150
35
145
40
140
45
135
50
130
55
125
60
VSS
PSTR[1]
PSTR[0]
PDWIN
VSS
D_INFO_WIN
DIS_INFO
VDD
VDD
\FFPN
VSS
MBFI
MBCLK
VDD
SCLK
VDCLK
VSS
SDRAM_DATA[63]
SDRAM_DATA[62]
SDRAM_DATA[61]
VDD
VDD
SDRAM_DATA[60]
SDRAM_DATA[59]
VSS
VSS
SDRAM_DATA[58]
VDD
SDRAM_DATA[57]
VSS
SDRAM_DATA[56]
VDD
SDRAM_DATA[55]
SDRAM_DATA[54]
VSS
SDRAM_DATA[53]
SDRAM_DATA[52]
VDD
SDRAM_DATA[51]
SDRAM_DATA[50]
VSS
SDRAM_DATA[49]
SDRAM_DATA[48]
VDD
SDRAM_DATA[47]
VDD
SDRAM_DATA[46]
SDRAM_DATA[45]
VSS
VSS
SDRAM_DATA[44]
VDD
SDRAM_DATA[43]
VDD
SDRAM_DATA[42]
SDRAM_DATA[41]
VSS
SDRAM_DATA[40]
VSS
SDRAM_DATA[39]
120
100
105
110
115
65
70
75
80
Figure 1. Pin Description
85
90
95
SDRAM_DATA[38]
VDD
SDRAM_DATA[37]
SDRAM_DATA[36]
SDRAM_DATA[35]
VSS
SDRAM_DATA[34]
SDRAM_DATA[33]
SDRAM_DATA[32]
VDD
VDD
CSN
RASN
CASN
WEN
VSS
BA0
SDRAM_ADDR[10]
SDRAM_ADDR[9]
SDRAM_ADDR[8]
VDD
SDRAM_ADDR[7]
SDRAM_ADDR[0]
VSS
VSS
VSS
MCLK
VDD
SDRAM_ADDR[6]
SDRAM_ADDR[1]
VDD
SDRAM_ADDR[5]
VDD
SDRAM_ADDR[2]
SDRAM_ADDR[4]
VSS
SDRAM_ADDR[3]
VSS
SDRAM_DATA[31]
SDRAM_DATA[30]
VDD
SDRAM_DATA[29]
SDRAM_DATA[28]
VSS
SDRAM_DATA[27]
SDRAM_DATA[26]
VDD
SDRAM_DATA[25]
SDRAM_DATA[24]
VDD
SDRAM_DATA[23]
VSS
SDRAM_DATA[22]
VDD
SDRAM_DATA[21]
VSS
SDRAM_DATA[20]
VDD
SDRAM_DATA[19]
VSS
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