PRELIMINARY
CY24212
MediaClock™
MPEG Clock Generator with VCXO
Features
• Integrated phase-locked loop (PLL)
• Low jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
Part Number
CY24212-1
CY24212-2
CY24212-3
CY24212-5
Outputs
1
2
2
2
Input Frequency Range
13.5 MHz/27 MHz (selectable)
13.5 MHz/27 MHz (selectable)
27 MHz
27 MHz
27 MHz
Two copies of 27 MHz
27 MHz/27.027 MHz (-1 ppm)
27 MHz/27.027 MHz (0 ppm)
Benefits
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Enables application compatibility
Output Frequencies
Logic Block Diagram
XIN
OSC
XOUT
Q
Φ
VCO
P
VCXO
OUTPUT
DIVIDERS
CLKA (27 MHz)
27 MHz (-2)
27/27.027 MHz (-3)
PLL
FSEL
VDD
VSS
Pin Configurations
CY24212-1
8-pin SOIC
XIN
VDD
VCXO
VSS
1
2
3
4
8
7
6
5
XOUT
VSS
FSEL
CLKA 27 MHz
XIN
VDD
VCXO
VSS
CY24212-2
8-pin SOIC
1
2
3
4
8
7
6
5
XOUT
CLKB 27 MHz
FSEL
CLKA 27 MHz
XIN
VDD
VCXO
VSS
CY24212-3,-5
8-pin SOIC
1
2
3
4
8
7
6
5
XOUT
CLKB (27/27.027 MHz)
FSEL
CLKA 27 MHz
Table 1. CY24212 (-1, -2) Frequency Select Option
FSEL
0
1
Reference
13.5 MHz
27 MHz
CLKA/CLKB
27 MHz
27 MHz
Table 2. CY24212 (-3, -5) Frequency Select Option
FSEL
0
1
Reference
27 MHz
27 MHz
CLKA
27 MHz
27 MHz
CLKB
27 MHz
27.027 MHz
Cypress Semiconductor Corporation
Document #: 38-07402 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 18, 2003
PRELIMINARY
Pin Description
Name
XIN
VDD
VCXO
VSS
CLKA
FSEL (-1,-2)
Pin Number Description
1
2
3
4
5
6
Reference Input.
Voltage Supply.
Input Analog Control for VCXO.
Ground.
27-MHz Clock Output.
Input Frequency Select, Weak Internal Pull-up.
FSEL = 0, XIN = 13.5 MHz
FSEL = 1, XIN = 27 MHz
Output Frequency Select, Weak Internal Pull-up.
FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz
FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz
Ground.
27 MHz.
27 MHz/27.027 MHz.
Reference Output.
CY24212
FSEL (-3,-5)
6
VSS (-1)
CLKB (-2)
CLKB (-3,-5)
XOUT
[1]
7
7
7
8
Pullable Crystal Specifications
Parameter
CR
load
C0/C1
ESR
T
o
Crystal Accuracy
TT
s
Equivalent Series Resistance
Operating Temperature
Crystal Accuracy
Stability over Temperature and Aging
0
35
Name
Crystal Load Capacitance
Min
Typ
14
240
50
70
+ 20
+ 50
Ω
°C
ppm
ppm
Max
Unit
pF
Absolute Maximum Conditions
Parameter
V
DD
T
S
T
J
Description
Supply Voltage
Storage Temperature
Digital Inputs
Electrostatic Discharge
[2]
Min
–0.5
–65
V
SS
– 0.3
2
Max
7.0
125
125
V
DD
+ 0.3
Unit
V
°C
°C
V
kV
Junction Temperature
Recommended Operating Conditions
Parameter
V
DD
T
A
C
LOAD
f
REF
Description
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Reference Frequency
13.5
Min
3.135
0
Typ
3.3
Max
3.465
70
15
27
Unit
V
°C
pF
MHz
Notes:
1. Float XOUT if XIN is externally driven.
2. Rated for ten years.
Document #: 38-07402 Rev. *B
Page 2 of 6
PRELIMINARY
DC Electrical Specifications
Parameter
I
OH
I
OL
C
IN
I
IH
I
IL
f
∆XO
V
VCXO
I
DD
V
IH
V
IL
R
UP
Name
Output High Current
Output Low Current
Input Capacitance
Input High Current
Input Low Current
VCXO Pullability Range
VCXO Input Range
Supply Current
Input High Voltage
Input Low Voltage
Pull-up resistor on inputs
Sum of Core and Output Current
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
V
DD
= 3.14 to 3.47V, measured V
IN
= 0V
100
0.7
V
IH
= V
DD
V
IL
= 0V
–
–
+150
0
5
–
Description
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
Min
12
12
Typ
24
24
CY24212
Max
Unit
mA
mA
7
10
50
V
DD
35
0.3
150
pF
µA
µA
ppm
V
mA
V
DD
V
DD
kΩ
AC Electrical Specifications (V
DD
= 3.3V)
Parameter
[3]
DC
ER
EF
t
9
t
10
Name
Output Duty Cycle
Rising Edge Rate
Falling Edge Rate
Clock Jitter
PLL Lock Time
Description
Duty Cycle is defined in
Figure 1,
50% of V
DD
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, C
LOAD
= 15 pF. See
Figure 2.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, C
LOAD
= 15 pF. See
Figure 2.
Peak-to-peak period jitter
Min
45
0.8
0.8
Typ
50
1.4
1.4
300
3
Max
55
Unit
%
V/ns
V/ns
ps
ms
Test and Measurement Set-up
V
DDs
0.1
µF
DUT
Outputs
C
LOAD
GND
Note:
3. Not 100% tested.
Document #: 38-07402 Rev. *B
Page 3 of 6
PRELIMINARY
Voltage and Timing Definitions
t
1
t
2
V
DD
50% of V
DD
Clock
Output
0V
CY24212
Figure 1. Duty Cycle Definition
t
3
t
4
V
DD
80% of V
DD
20% of V
DD
0V
Clock
Output
Figure 2. ER = (0.6 x V
DD
) /t3, EF = (0.6 x V
DD
) /t4
Ordering Information
Ordering Code
CY24212SC-1
CY24212SC-1T
CY24212SC-2
CY24212SC-2T
CY24212SC-3
CY24212SC-3T
CY24212SC-5
CY24212SC-5T
Package Name
S8
S8
S8
S8
S8
S8
S8
S8
Package Type
8-Pin SOIC
8-Pin SOIC -Tape and Reel
8-Pin SOIC
8-Pin SOIC -Tape and Reel
8-Pin SOIC
8-Pin SOIC -Tape and Reel
8-Pin SOIC
8-Pin SOIC -Tape and Reel
Operating Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Operating Voltage
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Document #: 38-07402 Rev. *B
Page 4 of 6
PRELIMINARY
Package Drawing and Dimensions
8-Lead (150-Mil) SOIC S8
CY24212
51-85066-*A
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-07402 Rev. *B
Page 5 of 6
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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