DSC533-05
Crystal-less™ Four output SAS Clock Generator
General Description
The DSC533-05 is a Crystal-less™, four
output clock generator that implements
Discera’s
proven
PureSilicon™
MEMS
technology. The device provides excellent
jitter and stability over a wide range of
supply voltages and temperatures.
By
eliminating the external quartz crystal,
MEMS
clock
generators
significantly
enhance reliability and accelerate product
development, while meeting stringent clock
performance criteria for a variety of
applications. The output frequencies in this
device are fixed and the outputs formats
may be factory configured to meet different
requirements such as LVCMOS, LVDS, HCSL
or LVPECL on any output independently.
DSC533-05 has an Output Enable / Disable
feature allowing it to disable all outputs
when OE1 and OE2 are low. See the OE
table 2 for more detail. The FS input select
line is for selecting the output frequency on
ClK0+/-. See table 1 for more details. The
device is available in a space saving 20 pin
QFN package.
Features
Four LVPECL (default) Outputs
o
o
o
o
125MHz LAN Clock
133.3333MHz Memory Clock
100MHz PCIe Clock
Pin Selectable SAS clock:
25MHz, or 150MHz
LVPECL, HCSL, LVDS, LVCMOS
Industrial: -40° to 85° C
Ext. commercial: -20° to 70° C
Available Format on any output:
o
o
o
Wide Temperature Range
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o
o
o
30% lower than competing devices
Qualified to MIL-STD-883
20 QFN
Excellent Shock & Vibration Immunity
Available Footprints:
Lead Free & RoHS Compliant
Block Diagram
Short Lead Time: 2 Weeks
AEC-Q100 Automotive Qualified
Applications
SAS, Sata, Fibre Channel Storage
Storage Area Networks
Server storage cards
Expansion cards
Direct Access Storage
_____________________________________________________________________________________________________________________________ _________________
DSC533-05
Page 1
DSC533-05
Crystal-less™ Four Output SAS Clock Generator
Specifications
(Unless specified otherwise: T=25° C,
VDD =3.3V)
Parameter
Supply Voltage
1
Condition
V
DD
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up on OE pin
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
T=25°C
Min.
2.25
Typ.
Max.
3.6
±100
±50
5
Unit
V
ppm
ms
V
ns
ns
kΩ
Frequency Stability
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Supply Current
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
3
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
0.75xV
DD
-
-
0.25xV
DD
5
20
40
148
155
-
V
DD
-1.55
800
250
LVPECL Outputs
I
DD
V
OH
V
OL
Output Enabled, R
L
=50Ω
R
L
=50Ω
Single-Ended
t
R
t
F
f
0
SYM
J
PER
J
PH
200kHz to 20MHz @133.3333MHz
100kHz to 20MHz @133.3333MHz
12kHz to 20MHz @133.3333MHz
20% to 80%
R
L
=50Ω, C
L
= 0pF
Each Output
Differential
2.3
48
2.5
0.25
0.38
1.7
76
1.125
350
200
2.3
48
2.5
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.28
0.4
1.7
460
52
V
DD
-1.08
-
mA
V
mV
ps
460
52
MHz
%
ps
RMS
ps
RMS
2
88
1.4
50
LVDS Outputs
Supply Current
Output offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time
3
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
Integrated Phase Noise
I
DD
V
OS
∆V
OS
Output Enabled, R
L
=100Ω
R=100Ω Differential
Single-Ended
20% to 80%
R
L
=50Ω, C
L
= 2pF
Single Frequency
Differential
mA
V
mV
mV
ps
MHz
%
ps
RMS
ps
RMS
V
PP
t
R
t
F
f
0
SYM
J
PER
J
PH
2
Notes:
1. Each V
DD
pin should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact
Sales@Discera.com
for alternate output options (LVPECL, LVDS, LVCMOS).
7. Contact
Sales@Discera.com
for alternative frequency options
_____________________________________________________________________________________________________________________________ _________________
DSC533-05
Page 2
DSC533-05
Crystal-less™ Four Output SAS Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Solder Reflow Profile
20-40
Sec
Temperature (°C)
217
°
C
200
°
C
.
ax
3C
/
Se
cM
ax
60-150
Sec
260
°
C
.
S
6C/
6C/
6C/
c
c
ec
Ma
Ma
Ma
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
.
.
x.
Pre heat
8 min max
Cool
Time
25
°
C
20 QFN
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
Peak Temperature
255-260°C
Time within 5°C of actual Peak
20-40 Sec
Ramp-Down Rate
6°C/Sec Max.
Time 25°C to Peak Temperature
8 min Max.
_____________________________________________________________________________________________________________________________ _________________
DSC533-05
Page 3
DSC533-05
Crystal-less™ Four Output SAS Clock Generator
Pin Description (20 QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD
NC
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD
FS
Pin Type
I
NA
Power
Power
O
O
O
O
Power
NA
I
NA
Power
Power
O
O
O
O
Power
I
Description
Output Enable; active high – See Table 2
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair; (default).
For LVCMOS setting, leave unconnected.
True output of differential pair or output of LVCMOS clock
SAS clock output - See table 1 for frequency selection
Complement output of differential pair; (default)
For LVCMOS setting, leave unconnected
True output of differential pair or output of LVCMOS clock
133.3333MHz
Power Supply, 3.3V.
Leave unconnected or grounded
Output Enable; active high – See Table 2
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair; (default)
In LVCMOS setting, leave unconnected.
True output of differential pair or output of LVCMOS clock
100MHz
Complement output of differential pair; (default)
For LVCMOS setting, leave unconnected
True output of differential pair or output of LVCMOS clock
125MHz
Power Supply
FS = 0, CLK0 = 150MHz;
FS = 1, CLK0 = 25MHz (LVCMOS Default)
–
–
–
-
_____________________________________________________________________________________________________________________________ _________________
DSC533-05
Page 4
DSC533-05
Crystal-less™ Four Output SAS Clock Generator
Table 1. Frequency Selection Table for CLK0+/-:
FS
0
1
CLK0+/- (MHz)
150
25
Pin Diagram (20
QFN)
CLK3+
CLK2+
16
CLK3-
20
OE1
NC
NC
VSS
1
2
3
4
5
19
18
17
15
14
13
12
11
VSS
NC
NC
OE2
6
7
8
9
10
CLK0+
CLK1+
CLK0-
CLK1-
20 QFN 5.0 x 3.2mm
_____________________________________________________________________________________________________________________________ _________________
DSC533-05
Page 5
VDD
NC
CLK2-
VDD
FS
微控制器 MCU
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