www.fairchildsemi.com
SPT5240
10-bit, 400 MWPS Current Output
Digital-to-Analog Converter
Features
• 400 MWPS update rate
• Complementary current outputs
• +3.3 V power supply
• Low power dissipation:
149mW (typ) @ƒ
CLK
= 400MHz and 12mA output
• Excellent AC performance:
SFDR = 58dBc for ƒ
CLK
= 400MHz and ƒ
OUT
= 1.27 MHz
• Internal reference
Description
The SPT5240 is a 10-bit digital-to-analog converter that
performs at an update rate of 400M words per second. The
architecture achieves excellent high-frequency performance
with very low power dissipation. This makes it ideal for all
types of battery-operated equipment requiring high-speed
digital-to-analog conversion.
The SPT5240 operates over an extended industrial
temperature range from -40°C to +85°C and is available in a
32-lead LQFP package.
Applications
• Battery-operated devices
• Portable RF devices
• Set top boxes
• Video displays
• Broadband RF
• High-speed test equipment
Functional Block Diagram
PWD
DV
DD
AV
DD
I
SET
Reference
Circuit
D0 – D9
10 Bits
10-bit
Current Output
DAC
IO
P
IO
N
CLK
DGND
AGND
REV. 1 June 2003
DATA SHEET
SPT5240
Electrical Specifications
(
T
A
= 25°C, AV
DD
= 3.3V, DV
DD
= 3.3V,
ƒ
OUT
= 1.27MHz,
ƒ
CLK
= 400MHz, Clock Duty Cycle = 50%,
I
OUT
= 20mA, R
L
= 50
Ω
; unless otherwise noted)
Parameter
DC Performance
Resolution
Differential Linearity Error (DLE)
Integral Linearity Error (ILE)
Offset Error
Full Scale Error
Gain Error
Maximum Full Scale Output Current
Output Compliance Voltage
Output Impedance
Gain Error Tempco
AC Performance
Maximum Clock Rate
Glitch Energy
Settling Time (t
settling
)
Output Rise Time
Output Fall Time
Output Delay Time (t
D
)
Spurious Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Digital and Clock Data Input
V
IH
Minimum
V
IL
Maximum
Logic “1” Current
Logic “0” Current
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Clock Feedthrough
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing
actually performed during production and Quality Assurance inspection.
LEVEL
I
IV
V
TEST PROCEDURE
100% production tested at the specified temperature.
Parameter is guaranteed by design or characterization data.
Parameter is a typical value for information purposes only.
See Figure 1
See Figure 1
V
V
I
I
V
V
V
-10
-10
1
1
-29
2
1
+10
+10
V
V
µ
A
µ
A
ns
ns
dBFS
See Figure 1
Major code transition
See Figure 1, major code trans.
IV
V
V
V
V
V
V
V
400
7
7.5
1.3
1.5
1.8
58
-55
MHz
pV-s
ns
ns
ns
ns
dBc
dBc
Full-scale output
DC at IO
N
DC at IO
N
DC at both outputs
DC at both outputs
DC at both outputs
I
I
I
I
I
V
V
V
V
-1
-4
-.005
-15
-15
30
1.5
250
±300
±1.34
10
2
4
+15
+15
Bits
LSB
LSB
%FS
%FS
mA
V
k
Ω
ppm
FS/°C
Conditions
Test Level
Min
Typ
Max Units
+.005 %FS
2
REV. 1 June 2003
SPT5240
DATA SHEET
Electrical Specifications
(Continued)
(
T
A
= 25°C, AV
DD
= 3.3V, DV
DD
= 3.3V,
ƒ
OUT
= 1.27MHz,
ƒ
CLK
= 400MHz, Clock Duty Cycle = 50%,
I
OUT
= 20mA, R
L
= 50
Ω
; unless otherwise noted)
Parameter
Power Supply Requirements
Supply Voltage
Supply Current Sleep Mode
AV
DD
DV
DD
Power Dissipation
25MHz Clock
25MHz Clock
20mA I
OUT
12mA I
OUT
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing
actually performed during production and Quality Assurance inspection.
LEVEL
I
IV
V
TEST PROCEDURE
100% production tested at the specified temperature.
Parameter is guaranteed by design or characterization data.
Parameter is a typical value for information purposes only.
V
V
IV
V
170
9.5
200
195
149
215
mA
µ
A
mW
mW
AV
DD
= DV
DD
IV
3.0
+3.3
3.6
V
Conditions
Test Level
Min
Typ
Max Units
REV. 1 June 2003
3
DATA SHEET
SPT5240
Absolute Maximum Ratings
(beyond which the device may be damaged)
Parameter
Supply Voltage
AV
DD
DV
DD
Voltage Difference between AGND and DGND
Voltage Difference between AV
DD
and DV
DD
Input Voltages
D0 – D9
CLK
Junction Temperature
Lead, soldering (10 seconds)
Storage Temperature
Thermal Resistance (
Θ
JA
) for 32 lead LQFP
-65
64
-0.5
-0.5
DV
DD
+0.5
DV
DD
+0.5
150
260
+150
V
V
°C
°C
°C
°C/W
-0.5
-0.5
3.7
3.7
0.5
0.5
V
V
V
V
Min
Max
Units
Note:
Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper
nominal applied conditions in typical applications.
4
REV. 1 June 2003
SPT5240
DATA SHEET
Typical Performance Characteristics
(
T
A
= 25°C, AV
DD
= 3.3V, DV
DD
= 3.3V,
ƒ
OUT
= 1.27MHz,
ƒ
CLK
= 400MHz, Clock Duty Cycle = 50%,
I
OUT
= 20mA, R
L
= 50
Ω
; unless otherwise noted)
AC Performance vs. Clock Frequency
65
60
55
50
THD
SNR
SFDR
AC Performance vs. Temperature
65
Clock frequency = 327MHz
SFDR
60
THD
55
dB
45
40
35
30
25
0
100
200
300
400
500
600
dB
50
SNR
45
40
-50
-25
0
25
50
75
Clock Frequency (MHz)
Temperature (°C)
AC Performance vs. V
DD
65
60
55
SFDR
Intergral Nonlinearity vs. Code
2.0
1.5
THD
50
45
40
35
3.0
3.3
3.6
SNR
LSB's
1.0
0.5
0
-0.5
0
128
256
384
512
640
768
896 1024
dB
V
DD
(V)
Differential Nonlinearity vs. Code
0.6
0.4
35
0.2
45
AV
DD
Code
AV
DD
, DV
DD
vs. Clock Frequency
LSB's
0
-0.2
-0.4
-0.6
0
128
256
384
512
640
768
896 1024
mA
25
15
DV
DD
5
40
105
205
245
328
400
Code
Clock (MHz)
REV. 1 June 2003
5
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