Sirenza Microdevices’ SVG-2066 is an IC based 6-bit digi-
tal 31.5dB range attenuator cascaded with a linear class A
amplifier in a low-cost surface-mountable 6x6 QFN plastic
package. This product is specifically designed as a high lin-
earity variable gain amplifier for infrastructure equipment
that can be used in either the RF transmit or RF receive
path. It features both parallel or serial programmability, pro-
grammable power up states, latchable parallel control, 3V
or 5V combatible logic and robust Class 1B ESD. The SVG-
2066 features configurable pin I/O’s for optimizing the part
over application specific bands.
500MHz - 2200MHz 6-Bit Variable Gain Amp
Pb
RoHS Compliant
&
Green
Package
6mm x 6mm QFN Package
Product Features
Functional Block Diagram
Serial or
Parallel Select
S-P
VDD
2 Bit Power Up
State Programming
U1 U2
Serial Interface
DATA
CLK
LE
VCC
RFIN
RFOUT
•
•
•
•
•
•
•
•
•
•
•
•
•
P1dB = 25dBm @ 2140MHz
OIP3 Typical 41dBm @ 2GHz
Gain = 15dB at 850MHz
31.5dB Attenuation range in 0.5dB steps
Serial or Parallel Controlled
Optional Latched Parallel Control
Programmable Power Up States
Immune to Latch-Up
Positive Supply Voltage
3V or 5V Logic Compatible
Applications
CDMA, W-CDMA Tx and Rx
GSM, EDGE Tx and Rx
High Performance VGA applications
Unit
MHz
dBm
Min.
500
24
23.5
25
15
9.5
11
39
39
41
5.9
6.9
9
9
12
12
320
100
115
70
130
7.9
13.5
Typ.
Max.
2200
P0.5 P1 P2 P4 P8 P16
6-Bit Parallel Interface
Key Specifications
Symbol
f
O
P
1dB
S
21
IP3
Parameters: Test Conditions, App circuit page 4
Z
0
= 50Ω, V
CC
= 5.0V, Vdd=3V, I = 115mA, T
L
= 30ºC
Frequency of Operation
Output Power at 1dB Compression – 850MHz
Output Power at 1dB Compression – 2.14GHz
Small Signal Gain – 850MHz @ 0dB state
Small Signal Gain – 2.14GHz @ 0dB state
Third Order Intercept (Pout = 9dBm per tone) - 850MHz
Third Order Intercept (Pout = 9dBm per tone) - 2.14GHz
Noise Figure at 850 MHz @ 0 dB state
Noise Figure at 2140 MHz @ 0 dB state
Input Return Loss 850-2200 MHz ( 0dB attenuation )
Output Return Loss 850-2200MHz ( 0dB attenuation )
10%/90% Settling time
Current (Vcc = 5V,Vdd=3v)
Thermal Resistance (junction - lead)
dB
dBm
NF
IRL
ORL
Ts
Icq
R
th, j-l
dB
dB
nS
mA
ºC/W
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product
for use in life-support devices and/or systems.
Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
1
http://www.sirenza.com
EDS-104432 Rev 3
Advanced Information
SVG-2066 500MHz-2200MHz 6-Bit VGA
Specification continued
Symbol
ERR
DYNR
FCLK
VDD
IDD
LH
LL
ILEAK
Parameters: Test Conditions
Z
0
= 50Ω, V
CC
= 5.0V,Vdd=3V Iq = 115mA
Atten setting accuracy any state (500MHz-2200MHz)
Attenuation dynamic range
Serial Data Clock Frequency
Drain voltage of Attenuator
Drain Supply Current
Digital Logic High
Digital Logic Low
Digital Logic Leakage
Unit
dB
dB
MHz
V
uA
V
V
uA
0.7xVDD
0
2.7
3.0
40
30.3
Min.
Typ.
+/- 0.2
31.5
Max.
+/- (0.2+3% Atten setting)
32.7
20
3.3
100
VDD
0.3xVDD
1
Absolute Maximum Ratings
Parameters
VCC Bias Current (I
C
)
VCC Bias Voltage
Power Dissipation
Drain Voltage (V
DD
)
Voltage on any Digital Input
Operating Lead Temperature (T
L
)
Max RF Input Power
Storage Temperature Range
Operating Junction Temperature (T
J
)
ESD Human Body Model
-40
-0.3
-0.3
-40
MIn
Max
220
8
1.5
4.0
VDD+0.3
+85
21
+150
+150
500
Unit
mA
V
W
V
V
ºC
dBm
ºC
ºC
V
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Operation of this device beyond any one of these limits may cause perma-
nent damage. For reliable continuous operation the device voltage and
current must not exceed the maximum operating values specified in the
table on page one.
Bias conditions should also satisfy the following expression:
I
D
V
D
< (T
J
- T
L
) / R
TH’
j-l
Digital Interfacing:
Serial or Parallel Mode Selection
The SVG-2066 can be controlled with either a serial or parallel interface. The S-P bit selects the mode: S-P=low for parallel mode
and S-P=high for serial mode.
Parallel Mode Operation
For latched parallel interfacing the LE line should be held low while changing attenuation state control logic P0.5 thru P16. To load
data pulse LE from low to high and to low again. See Figure 1 and Table 1 on the next page for the parallel mode timing diagram
and specifications. For direct parallel mode operation the LE line should be held high and the attenuation state is directly loaded
when the parallel line logic changes. The truth table for parallel operation is shown in Table 2.
Serial Mode Operation
Three CMOS compatible signals control the attenuator in this mode: DATA, CLK and LE. When LE is high the latch is enabled and
data in the serial shift register gets loaded. When the LE is low the data in the shift register is latched. Refer to Figure 2 for the tim-
ing diagram and Table 3 for the timing specifications.
Power up State Programming
At power up in serial mode the six control bits are set to the values available on the six parallel inputs P0.5 thru P16 (see Table 2).
For parallel mode the power up state is set with the two bit word defined by U1 and U2. See the truth table in Table 4.
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