0
R
QPro Series Configuration PROMs
(XQ) including
Radiation-Hardened Series (XQR)
2
DS062 (v3.1) November 5, 2001
0
Preliminary Product Specification
Features
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XQ1701L/XQR1701L
QML Certified
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
Simple interface to the FPGA; requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Supports XQ4000XL/Virtex fast configuration mode
(15.0 MHz)
Available in 44-pin ceramic LCC (M grade) package
Available in 20-pin SOIC package (XQ1701L only)
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Allianc™ and
Foundation™ series software packages.
XQR1701L (only)
Fabricated on Epitaxial Silicon to improve latch
performance (parts are immune to Single Event
Latch-up)
Single Event Bit Upset immune
Total Dose tolerance in excess of 50 krad(Si)
All lots subjected to TID Lot Qualification in accordance
with method 1019 (dose rate ~9.0 rad(Si)/sec)
XQ1701L (only)
Also available under the following Standard Microcircuit
Drawing (SMD): 5962-9951401. For more information
contact hte Defense Supply Center Columbus (DSCC):
http://www.dscc.dla.mil/Programs/Smcr/
Description
The QPro™ series XQ1701L are Xilinx 3.3V high-density
configuration PROMs. The XQR1701L are radiation hard-
ened. These devices are manufactured on Xilinx QML certi-
fied manufacturing lines utilizing epitaxial substrates and
TID lot qualification (per method 1019).
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Figure 1
shows a simplied block diagram.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
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© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS062 (v3.1) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
R
VCC
VPP
GND
RESET/
OE
or
OE/
RESET
CE
CEO
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1:
Simplified Block Diagram (does not show programming circuit)
Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I
CC
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The polar-
ity of this input pin is programmable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
the pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at "0", and puts the DATA output in a
high-impedance state. The polarity of this input is program-
mable. The default is active High RESET, but the preferred
option is active Low RESET, because it can be driven by the
FPGAs INIT pin.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ-
ent methods to invert this pin.
V
PP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin must be connected to V
CC
. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
V
PP
floating!
V
CC
and GND
Positive supply and ground pins.
2
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1-800-255-7778
DS062 (v3.1) November 5, 2001
Preliminary Product Specification
R
QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
•
44-Pin CLCC
2
5
19
21
3, 24
27
41
44
•
•
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
CC
glitch.
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset. This may not be a safe
assumption.
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the D
IN
pin.
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
PROM Pinouts
Pin Name
DATA
CLK
RESET/OE (OE/RESET)
CE
GND
CEO
V
PP
V
CC
Capacity
Devices
XQR1701L
XQ1701L
Configuration Bits
1,048,576
1,048,576
Xilinx FPGAs and Compatible PROMs.
Device
XQ(R)4013XL
XQ(R)4036XL
XQ(R)4062XL
XQ(R)4013XL
XQ(R)4036XL
XQ(R)4062XL
XQV(R)300
XQV(R)600
XQV(R)1000
Configuration Bits
393,632
832,528
1,433,864
393,632
832,528
1,433,864
1,751,840
3,608,000
6,127,776
XQ(R)1701L
PROMs
1
1
2
1
1
2
2
4
6
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the PROM is
read sequentially, accessed via the internal address and bit
counters which are incremented on every valid rising edge
of CCLK.
If the user-programmable, dual-function D
IN
pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.
Controlling PROMs
Connecting the FPGA device with the PROM.
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The DATA output(s) of the of the PROM(s) drives the
D
IN
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
DS062 (v3.1) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
3
QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
R
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the remaining data in the PROM and inter-
prets it as preamble, length count etc. Since the FPGA is
the master, it issues the necessary number of CCLK pulses,
up to 16 million (2
24
) and DONE goes High. However, the
FPGA configuration will be completely wrong, with potential
contentions inside the FPGA and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded PROMs provide additional memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See
Figure 2.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA RESET pin goes
Low, assuming the PROM reset polarity option has been
inverted.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of D
IN
.
4
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1-800-255-7778
DS062 (v3.1) November 5, 2001
Preliminary Product Specification
R
QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
Vcc
DOUT
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
VCC
FPGA
MODES*
3.3V
4.7K
VPP
VCC
DATA
CLK
CE
OE/RESET
VPP
DATA
DIN
RESET
RESET
CCLK
DONE
INIT
* For mode pin connections,
refer to the appropriate FPGA data sheet.
PROM
CEO
CLK
CE
Cascaded
Serial
Memory
OE/RESET
(Low Resets the Address Pointer)
CCLK
(Output)
D
IN
D
OUT
(Output)
DS027_02_060100
Figure 2:
Master Serial Mode.
The one-time-programmable PROM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
DS062 (v3.1) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
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