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CYD04S72V18-200BBXC: 产品描述sram 4M sync dual port 64kx72 90nm com; 产品类别存储存储; 文件大小1MB，共52页; 制造商Cypress(赛普拉斯); 标准

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CYD04S72V18-200BBXC概述

sram 4M sync dual port 64kx72 90nm com

CYD04S72V18-200BBXC规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Cypress(赛普拉斯)
零件包装代码	BGA
包装说明	23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484
针数	484
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	3.3 ns
JESD-30 代码	S-PBGA-B484
JESD-609代码	e1
长度	23 mm
内存密度	4718592 bit
内存集成电路类型	DUAL-PORT SRAM
内存宽度	72
湿度敏感等级	3
功能数量	1
端子数量	484
字数	65536 words
字数代码	64000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64KX72
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	SQUARE
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	2.16 mm
最大供电电压 (Vsup)	1.58 V
最小供电电压 (Vsup)	1.42 V
标称供电电压 (Vsup)	1.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	40
宽度	23 mm
Base Number Matches	1

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FullFlex

FullFlex™ Synchronous SDR Dual Port SRAM

Features

■

Functional Description

The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,

9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static

RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two

ports are provided, enabling simultaneous access to the array.

Simultaneous access to a location triggers deterministic access

control. For FullFlex72 these ports operate independently with

72-bit bus widths and each port is independently configured for

two pipelined stages. Each port is also configured to operate in

pipelined or flow through mode.

The advanced features include the following:

■

True dual port memory enables simultaneous access to the

shared array from each port

Synchronous pipelined operation with Single Data Rate (SDR)

operation on each port

❐

SDR interface at 200 MHz

❐

Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)

Selectable pipelined or flow-through mode

1.5V or 1.8V core power supply

Commercial and Industrial temperature

IEEE 1149.1 JTAG boundary scan

Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and

x18) packages

FullFlex72 family

❐

36 Mbit: 512K x 72 (CYD36S72V18)

❐

18 Mbit: 256K x 72 (CYD18S72V18)

❐

9 Mbit: 128K x 72 (CYD09S72V18)

❐

4 Mbit: 64K x 72 (CYD04S72V18)

FullFlex36 family

❐

36 Mbit: 1M x 36 (CYD36S36V18)

❐

18 Mbit: 512K x 36 (CYD18S36V18)

❐

9 Mbit: 256K x 36 (CYD09S36V18)

❐

4 Mbit: 128K x 36 (CYD04S36V18)

❐

2 Mbit: 64K x 36 (CYD02S36V18)

FullFlex18 family

❐

36 Mbit: 2M x 18 (CYD36S18V18)

❐

18 Mbit: 1M x 18 (CYD18S18V18)

❐

9 Mbit: 512K x 18 (CYD09S18V18)

❐

4 Mbit: 256K x 18 (CYD04S18V18)

Built in deterministic access control to manage address colli-

sions

❐

Deterministic flag output upon collision detection

❐

Collision detection on back-to-back clock cycles

❐

First Busy Address readback

Advanced features for improved high speed data transfer and

flexibility

❐

Variable Impedance Matching (VIM)

❐

Echo clocks

❐

Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V

LVCMOS, or 2.5V LVCMOS IO on each port

❐

Burst counters for sequential memory access

❐

Mailbox with interrupt flags for message passing

❐

Dual Chip Enables for easy depth expansion

■

Built in deterministic access control to manage address colli-

sions during simultaneous access to the same memory location

Variable Impedance Matching (VIM) to improve data trans-

mission by matching the output driver impedance to the line

impedance

Echo clocks to improve data transfer

■

To reduce the static power consumption, chip enables power

down the internal circuitry. The number of latency cycles before

a change in CE0 or CE1 enables or disables the databus

matches the number of cycles of read latency selected for the

device. For a valid write or read to occur, activate both chip

enable inputs on a port.

Each port contains an optional burst counter on the input address

address, the counter increments the address internally.

Additional device features include a mask register and a mirror

counter interrupt (CNTINT) flags notify the host that the counter

reaches maximum count value on the next clock cycle. The host

reads the burst counter internal address, mask register address,

and busy address on the address lines. The host also loads the

counter with the address stored in the mirror register by using the

retransmit functionality. Mailbox interrupt flags are used for

message passing, and JTAG boundary scan and asynchronous

Master Reset (MRST) are also available. The

Logic Block

Diagram

on page 2 shows these features.

The FullFlex72 is offered in a 484-Ball plastic BGA package. The

FullFlex36 and FullFlex18 are available in 256-Ball fine pitch

BGA package.

■

Cypress Semiconductor Corporation

Document Number: 38-06082 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised May 15, 2008

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CYD04S72V18-200BBXC

CYD04S72V18-200BBXC概述

CYD04S72V18-200BBXC规格参数

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