CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EZ-USB FX2LP™ USB Microcontroller
High Speed USB Peripheral Controller
Features (CY7C68013A/14A/15A/16A)
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USB 2.0 USB IF High Speed Certified (TID # 40460272)
Single Chip Integrated USB 2.0 Transceiver, Smart SIE, and
Enhanced 8051 Microprocessor
Fit, Form, and Function Compatible with the FX2
❐
Pin compatible
❐
Object code compatible
❐
Functionally compatible (FX2LP is a superset)
Ultra Low Power: I
CC
No More than 85 mA in any Mode
❐
Ideal for bus and battery powered applications
Software: 8051 Code Runs from:
❐
Internal RAM, which is downloaded through USB
❐
Internal RAM, which is loaded from EEPROM
❐
External memory device (128 pin package)
16 KBytes of On-Chip Code/Data RAM
Four Programmable BULK, INTERRUPT, and
ISOCHRONOUS Endpoints
❐
Buffering options: double, triple, and quad
Additional Programmable (BULK/INTERRUPT) 64 Byte
Endpoint
8-Bit or 16-Bit External Data Interface
Smart Media Standard ECC Generation
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GPIF (General Programmable Interface)
❐
Enables direct connection to most parallel interfaces
❐
Programmable waveform descriptors and configuration
registers to define waveforms
❐
Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
Integrated, Industry Standard Enhanced 8051
❐
48 MHz, 24 MHz, or 12 MHz CPU operation
❐
Four clocks per instruction cycle
❐
Two USARTs
❐
Three counter/timers
❐
Expanded interrupt system
❐
Two data pointers
3.3V Operation with 5V Tolerant Inputs
Vectored USB Interrupts and GPIF/FIFO Interrupts
Separate Data Buffers for the Setup and Data Portions of a
CONTROL Transfer
Integrated I
2
C Controller, Runs at 100 or 400 kHz
Four Integrated FIFOs
❐
Integrated glue logic and FIFOs lower system cost
❐
Automatic conversion to and from 16-bit buses
❐
Master or slave operation
❐
Uses external clock or asynchronous strobes
❐
Easy interface to ASIC and DSP ICs
Available in Commercial and Industrial Temperature Grade
(all packages except VFBGA)
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Cypress Semiconductor Corporation
Document #: 38-08032 Rev. *P
•198 Champion Court•
San Jose, CA 95134-1709•
408-943-2600
Revised October 12, 2009
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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Logic Block Diagram
24 MHz
Ext. XTAL
High performance micro
using standard tools
with lower-power options
Address (16)
Data (8)
FX2LP
Address (16) / Data Bus (8)
VCC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
Master
Additional I/Os (24)
I
2
C
1.5k
connected for
full speed
D+
D–
Integrated
full speed and
high speed
XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
16 KB
RAM
Abundant I/O
including two USARTs
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
ECC
RDY (6)
CTL (6)
4 kB
FIFO
8/16
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Features (CY7C68013A/14A only)
■
CY7C68014A: Ideal for Battery Powered Applications
❐
Suspend current: 100
μA
(typ)
CY7C68013A: Ideal for Non Battery Powered Applications
❐
Suspend current: 300
μA
(typ)
Available in Five Pb-free Packages with Up to 40 GPIOs
❐
128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin
VFBGA (24 GPIOs)
Cypress has created a cost effective solution that provides
superior time-to-market advantages with low power to enable
bus powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second, the maximum allowable
USB 2.0 bandwidth, while still using a low cost 8051
microcontroller in a package as small as a 56 VFBGA (5 mm x 5
mm). Because it incorporates the USB 2.0 transceiver, the
FX2LP is more economical, providing a smaller footprint solution
than USB 2.0 SIE or external transceiver implementations. With
EZ-USB FX2LP, the Cypress Smart SIE handles most of the
USB 1.1 and 2.0 protocol in hardware, freeing the embedded
microcontroller for application specific functions and decreasing
development time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form and function
compatible with the 56, 100, and 128 pin FX2.
Five packages are defined for the family: 56VFBGA, 56 SSOP,
56 QFN, 100 TQFP, and 128 TQFP.
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■
Features (CY7C68015A/16A only)
■
CY7C68016A: Ideal for Battery Powered Applications
❐
Suspend current: 100
μA
(typ)
CY7C68015A: Ideal for Non Battery Powered Applications
❐
Suspend current: 300
μA
(typ)
■
Available in Pb-free 56-pin QFN Package (26 GPIOs)
❐
Two more GPIOs than CY7C68013A/14A enabling additional
features in same footprint
Cypress’s EZ-USB FX2LP™ (CY7C68013A/14A) is a low power
version of the EZ-USB FX2™ (CY7C68013), which is a highly
integrated, low power USB 2.0 microcontroller. By integrating the
USB 2.0 transceiver, serial interface engine (SIE), enhanced
8051 microcontroller, and a programmable peripheral interface
in a single chip,
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Document #: 38-08032 Rev. *P
Page 2 of 62
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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
1. Applications
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Figure 2-1. Crystal Configuration
C1
12 pf
24 MHz
C2
12 pf
Portable video recorder
MPEG/TV conversion
DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Cameras
Scanners
Home PNA
Wireless LAN
MP3 players
Networking
20 × PLL
12 pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
The CLKOUT pin, which can be three-stated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.
2.2.2 USARTs
FX2LP contains two standard 8051 USARTs, addressed through
Special Function Register (SFR) bits. The USART interface pins
are available on separate I/O pins, and are not multiplexed with
port pins.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and
12 MHz) such that it always presents the correct frequency for
230 KBaud operation.
[1]
2.2.3 Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX2LP functions. These SFR additions are
shown in
Table 2-1
on page 4. Bold type indicates non standard,
enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit addressable registers. The four I/O ports A to
D use the SFR addresses used in the standard 8051 for ports 0
to 3, which are not implemented in FX2LP. Because of the faster
and more efficient SFR addressing, the FX2LP I/O ports are not
addressable in external RAM space (using the MOVX
instruction).
The “Reference Designs” section of the
Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Visit
www.cypress.com
for more information.
2. Functional Overview
2.1 USB Signaling Speed
FX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
■
■
Full speed, with a signaling bit rate of 12 Mbps
High speed, with a signaling bit rate of 480 Mbps.
FX2LP does not support the low speed signaling mode of
1.5 Mbps.
2.2 8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
2.2.1 8051 Clock Frequency
FX2LP has an on-chip oscillator circuit that uses an external
24 MHz (±100 ppm) crystal with the following characteristics:
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2.3 I
2
C Bus
FX2LP supports the I
2
C bus as a master only at 100/400 KHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I
2
C
device is connected.
Parallel resonant
Fundamental mode
500
μW
drive level
12 pF (5% tolerance) load capacitors
2.4 Buses
All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,
multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY and internal counters divide
it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
Note
1. 115 KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
Document #: 38-08032 Rev. *P
Page 3 of 62
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CY7C68015A, CY7C68016A
Table 2-1. Special Function Registers
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x
IOA
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
9x
IOB
EXIF
MPAGE
Ax
IOC
INT2CLR
INT4CLR
Bx
IOD
IOE
OEA
OEB
OEC
OED
OEE
IP
EP01STAT
GPIFTRIG
GPIFSGLDATH
GPIFSGLDATLX
GPIFSGLDATLNOX
T2CON
RCAP2L
RCAP2H
TL2
TH2
EICON
EIE
EIP
Cx
SCON1
SBUF1
Dx
PSW
Ex
ACC
Fx
B
SCON0
SBUF0
AUTOPTRH1
AUTOPTRL1
reserved
AUTOPTRH2
AUTOPTRL2
reserved
IE
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
AUTOPTRSET-UP
2.5 USB Boot Methods
During the power up sequence, internal logic checks the I
2
C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
in place of the internally stored values (0xC0), or it boot-loads the
EEPROM contents into internal RAM (0xC2). If no EEPROM is
detected, FX2LP enumerates using internally stored descriptors.
The default ID values for FX2LP are VID/PID/DID (0x04B4,
0x8613, 0xAxxx where xxx = Chip revision).
[2]
Table 2-2. Default ID Values for FX2LP
Vendor ID
Product ID
Device release
Default VID/PID/DID
0x04B4 Cypress Semiconductor
0x8613 EZ-USB FX2LP
0xAnnn Depends on chip revision
(nnn = chip revision where first
silicon = 001)
Two control bits in the USBCS (USB Control and Status) register,
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0, the
Default USB Device handles device requests; if RENUM = 1, the
firmware services the requests.
2.7 Bus-Powered Applications
The FX2LP fully supports bus powered designs by enumerating
with less than 100 mA as required by the USB 2.0 specification.
2.8 Interrupt System
2.8.1 INT2 Interrupt Request and Enable Registers
FX2LP implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.
2.8.2 USB Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that is required to identify the
individual USB interrupt source, the FX2LP provides a second
level of interrupt vectoring, called Autovectoring. When a USB
interrupt is asserted, the FX2LP pushes the program counter to
its stack, and then jumps to the address 0x0043 where it expects
to find a “jump” instruction to the USB Interrupt service routine.
2.6 ReNumeration
Because the FX2LP’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
When first plugged into USB, the FX2LP enumerates
automatically and downloads firmware and USB descriptor
tables over the USB cable. Next, the FX2LP enumerates again,
this time as a device defined by the downloaded information.
This patented two step process called ReNumeration™ happens
instantly when the device is plugged in, without a hint that the
initial download step has occurred.
Note
2. The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document #: 38-08032 Rev. *P
Page 4 of 62
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CY7C68015A, CY7C68016A
The FX2LP jump instruction is encoded as follows:
Table 2-3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
INT2VEC Value
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
EP2ISOERR
EP4ISOERR
EP6ISOERR
EP8ISOERR
reserved
reserved
ISO EP2 OUT PID sequence error
ISO EP4 OUT PID sequence error
ISO EP6 OUT PID sequence error
ISO EP8 OUT PID sequence error
EP0PING
EP1PING
EP2PING
EP4PING
EP6PING
EP8PING
ERRLIMIT
EP0-IN
EP0-OUT
EP1-IN
EP1-OUT
EP2
EP4
EP6
EP8
IBN
SUDAV
SOF
SUTOK
SUSPEND
USB RESET
HISPEED
EP0ACK
Source
Setup Data Available
Start of Frame (or microframe)
Setup Token Received
USB Suspend request
Bus reset
Entered high speed operation
FX2LP ACK’d the CONTROL Handshake
reserved
EP0-IN ready to be loaded with data
EP0-OUT has USB data
EP1-IN ready to be loaded with data
EP1-OUT has USB data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN-Bulk-NAK (any IN endpoint)
reserved
EP0 OUT was Pinged and it NAK’d
EP1 OUT was Pinged and it NAK’d
EP2 OUT was Pinged and it NAK’d
EP4 OUT was Pinged and it NAK’d
EP6 OUT was Pinged and it NAK’d
EP8 OUT was Pinged and it NAK’d
Bus errors exceeded the programmed limit
Notes
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high
byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs
the jump to the correct address out of the 27 addresses within the page.
2.8.3 FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual
FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring.
Table 2-4
on page 6 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
Document #: 38-08032 Rev. *P
Page 5 of 62
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