Latch-up Current...................................................... >200 mA
Operating Range
Device
CY62157DV30L
CY62157DV30LL
CY62157DV30L
Automotive –40°C to +125°C
(Preliminary)
Range
Industrial
Ambient
Temperature (T
A
) V
CC
[10]
–40°C to +85°C
2.20V
to
3.60V
Electrical Characteristics
Over the Operating Range
CY62157DV30
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1mA
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
Industrial
Automotive
Output Leakage Current GND < V
O
< V
CC
, Output
Disabled
V
CC
Operating Supply
Current
f = f
MAX
= 1/t
RC
f = 1 MHz
I
SB1
Automatic CE
Power-Down
Current — CMOS
Inputs
CE
1
> V
CC
−0.2V,
CE
2
< 0.2V Industrial
V
IN
>V
CC
–0.2V, V
IN
<0.2V)
f = f
MAX
(Address and Data
Automotive
Only),
f = 0 (OE, WE, BHE and
BLE), V
CC
=3.60V
CE
1
> V
CC
– 0.2V or CE
2
<
0.2V,
V
IN
> V
CC
– 0.2V or V
IN
<
0.2V,
f = 0, V
CC
= 3.60V
Industrial
Automotive
Industrial
Automotive
V
CC
= V
CCmax
L
I
OUT
= 0 mA
LL
CMOS levels
L
LL
L
LL
L
2
2
Test Conditions
V
CC
= 2.20V
V
CC
= 2.70V
V
CC
= 2.20V
V
CC
= 2.70V
1.8
2.2
–0.3
–0.3
–1
-4
–1
-4
12
Min.
2.0
2.4
0.4
0.4
V
CC
+ 0.3V
V
CC
+ 0.3V
0.6
0.8
+1
+4
+1
+4
20
15
1.5
3
3
20
8
50
Typ.
[2]
Max.
Unit
V
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
µA
I
SB2
Automatic CE
Power-Down
Current — CMOS
Inputs
L
LL
L
2
2
20
8
50
µA
Notes:
8. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
9. V
IH(max)
= V
CC
+0.75V for pulse duration less than 20 ns.
10. Full device AC operation assumes a 100
µs
ramp time from 0 to V
cc
(min) and 200
µs
wait time after V
cc
stabilization.
Document #: 38-05392 Rev. *E
Page 3 of 12
CY62157DV30
MoBL
®
Capacitance
[11, 12]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
10
10
Unit
pF
pF
Thermal Resistance
[11]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
BGA
72
8.86
TSOP II
75.13
8.95
TSOP I
74.88
8.6
Unit
°C/W
°C/W
AC Test Loads and Waveforms
[13]
V
CC
OUTPUT
30 pF / 50 pF
R1
V
CC
GND
R2
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Industrial (L)
Industrial (LL)
Automotive (L)
0
t
RC
Conditions
Min.
1.5
10
4
25
ns
ns
Typ.
[2]
Max.
Unit
V
µA
t
CDR[11]
t
R[14]
Chip Deselect to Data
Retention Time
Operation Recovery Time
Notes:
11. Tested initially and after any design or process changes that may affect these parameters.
12. The input capacitance on the CE
2
pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF.
13. Test condition for the 45 ns part is a load capacitance of 30 pF.
14. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100 us or stable at V
CC(min.)
> 100 us.
Document #: 38-05392 Rev. *E
Page 4 of 12
CY62157DV30
MoBL
®
Data Retention Waveform
[15]
V
CC
CE
1
or
BHE
.
BLE
V
CC
, min.
t
CDR
DATA RETENTION MODE
V
DR
> 1.5 V
V
CC
, min.
t
R
or
CE
2
Switching Characteristics
Over the Operating Range
[16]
45 ns
[13]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Cycle
[19]
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[17, 18]
WE HIGH to Low-Z
[17]
10
45
40
40
0
0
35
40
25
0
15
10
55
40
40
0
0
40
40
25
0
20
10
70
60
60
0
0
45
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[17]
OE HIGH to High
Z
[17, 18]
Z
[17]
Z
[17, 18]
0
45
45
10
15
10
20
10
20
0
55
55
10
25
CE
1
LOW and CE
2
HIGH to Low
CE
1
HIGH and CE
2
LOW to High
5
15
10
20
0
70
70
10
45
25
5
20
10
25
45
45
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
55 ns
Min.
Max.
70 ns
Min.
Max.
Unit
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH and CE
2
LOW to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z
[17]
BLE / BHE HIGH to HIGH
Z
[17, 18]
Notes:
15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
16. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
17. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
18. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedence state.
19. The internal Write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity DAC0832 is
port(clk:in std_logic; ......
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