power consumption by 99% when addresses are not toggling.
The device can also be put into standby mode when deselect-
ed (CE HIGH or both BLE and BHE are HIGH). The input/out-
put pins (I/O
0
through I/O
15
) are placed in a high-impedance
state when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are dis-
abled (BHE, BLE HIGH), or during a write operation (CE LOW,
and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The CY62137CV18 is available in a 48-ball FBGA package.
•
•
•
•
Functional Description
The CY62137CV18 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
ROW DECODER
SENSE AMPS
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
128K x 16
RAM Array
2048 X 1024
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
A
11
A
12
A
13
A
14
A
15
Power -Down
Circuit
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-05017 Rev. *B
•
3901 North First Street
A
16
•
San Jose
•
CA 95134 • 408-943-2600
Revised October 31, 2001
CY62137CV18 MoBL2™
Pin Configuration
[1, 2]
FBGA
Top View
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
3
A
0
A
3
A
5
NC
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
ccq
V
ssq
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
I/O
12
DNU
I/O
13
NC
A
8
A
14
A
12
A
9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage to Ground Potential
.................−0.2V
to +2.4V
DC Voltage Applied to Outputs
in High Z State
[3]
....................................... −0.2V
to V
CC
+ 0.2V
DC Input Voltage
[3]
.................................... −0.2V
to V
CC
+ 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Device
CY62137CV18
Range
Industrial
Ambient Temperature
−40°C
to +85°C
V
CC
1.65V to 1.95V
Product Portfolio
Power Dissipation (Industrial)
Operating (I
CC
)
V
CC
Range
Product
CY62137CV18
V
CC(min.)
V
CC(typ.)
[4]
1.65V
1.80V
V
CC(max.)
1.95V
Speed
55 ns
70 ns
f = 1 MHz
Typ.
[4]
0.5 mA
0.5 mA
Max.
2 mA
2 mA
f = f
max
Typ.
[4]
2 mA
1.5 mA
Max.
7 mA
6 mA
Standby (I
SB2
)
Typ.
[4]
1
µA
Max.
8
µA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or V
SS
to ensure proper application.
3. V
IL
(min) =
−
2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
Document #: 38-05017 Rev. *B
Page 2 of 11
CY62137CV18 MoBL2™
Electrical Characteristics
Over the Operating Range
CY62137CV18-55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current GND < V
I
< V
CC
Output Leakage
Current
V
CC
Operating Supply
Current
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
GND < V
O
< V
CC
, Output Dis-
abled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 1.95V
I
OUT
= 0 mA
CMOS levels
Test Conditions
I
OH
=
−0.1
mA
I
OL
= 0.1 mA
V
CC
= 1.65V
V
CC
= 1.65V
1.4
−0.2
−1
−1
2
0.5
1
Min. Typ.
[4]
1.4
0.2
V
CC
+
0.2V
0.4
+1
+1
7
2
8
1.4
−0.2
−1
−1
1.5
0.5
1
Max.
CY62137CV18-70
Min.
1.4
0.2
V
CC
+
0.2V
0.4
+1
+1
6
2
8
Typ.
[4]
Max.
Unit
V
V
V
V
µA
µA
mA
mA
µA
I
CC
I
SB1
CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V, V
IN
< 0.2V
f = f
MAX
(Address and Data Only),
f = 0 (OE, WE, BHE, and BLE)
CE > V
CC
−
0.2V
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 1.95V
I
SB2
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
(Junction to Ambient)
[5]
Thermal Resistance
(Junction to Case)
[5]
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
Symbol
Θ
JA
Θ
JC
BGA
55
16
Unit
°C/W
°C/W
Document #: 38-05017 Rev. *B
Page 3 of 11
CY62137CV18 MoBL2™
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
GND
30 pF
INCLUDING
JIG AND
SCOPE
R2
Rise Time:
1 V/ns
Fall Time:
1 V/ns
V
CC
Typ
10%
ALL INPUT PULSES
90%
90%
10%
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
R1
R2
R
TH
V
TH
1.8V
13500
10800
6000
0.80
UNIT
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[5]
t
R[6]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= 1.0V
CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
0
t
RC
Conditions
Min.
1.0
0.5
Typ.
[4]
Max.
1.95
5
Unit
V
µA
ns
ns
Data Retention Waveform
[7]
DATA RETENTION MODE
V
CC
V
CC(min.)
t
CDR
V
DR
> 1.0 V
V
CC(min.)
t
R
CE or
BHE.BLE
Notes:
6.
7.
Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
>
100
µ
s or stable at V
CC(min)
>
100
µ
s.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05017 Rev. *B
Page 4 of 11
CY62137CV18 MoBL2™
Switching Characteristics
Over the Operating Range
[8]
55 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[9]
OE HIGH to High Z
[9, 10]
CE LOW to Low Z
[9]
CE HIGH to High Z
[9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[9]
BLE/BHE HIGH to High Z
[9, 10]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9, 10]
WE HIGH to Low Z
[9]
5
55
40
40
0
0
40
40
25
0
20
10
5
20
70
60
60
0
0
50
60
30
0
25
0
55
55
5
25
5
20
0
70
70
5
20
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
70 ns
Max.
Unit
WRITE CYCLE
[11]
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and output loading of the
specified I
OL
/I
OH
and 30 pF load capacitance.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
