Electronics
Semiconductor Division
RC2211
FSK Demodulator/Tone Decoder
Features
¥
¥
¥
¥
¥
¥
¥
Wide frequency range Ð 0.01 Hz to 300 kHz
Wide supply voltage range Ð 4.5V to 20V
DTL/TTL/ECL logic compatibility
FSK demodulation with carrier-detector
Wide dynamic range Ð 2 mV to 3 V
RMS
Adjustable tracking range Ð
±
1% to
±
80%
Excellent temperature stability Ð 20 ppm/
°
C typical
Applications
¥
¥
¥
¥
¥
FSK demodulation
Data synchronization
Tone decoding
FM detection
Carrier detection
Description
The RC2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications. It is
particularly well-suited for FSK modem applications, and
operates over a wide frequency range of 0.01 Hz to 300 kHz.
It can accommodate analog signals between 2 mV and 3V,
and can interface with conventional DTL, TTL and ECL
logic families. The circuit consists of a basic PLL for
tracking an input signal frequency within the passband, a
quadrature phase detector which provides carrier detection,
and an FSK voltage comparator which provides FSK
demodulation. External components are used to indepen-
dently set carrier frequency, bandwidth and output delay.
Block Diagram
Loop Filter
f-Detector
FSK
Comparator
VCO
f
Preamp
Lock
Detector
Outputs
Lock
Detector
Filter
Lock
Detector
Comparator
65-2211-01
Data Filter
FSK
Data
Output
f
FSK
Input
f-Detector
Rev. 1.0.1
This document was created with FrameMaker 4 0 4
PRODUCT SPECIFICATION
RC2211
Description of Circuit Controls
Signal Input
(Pin 2)
The input signal is AC coupled to this terminal. The internal
impedance at pin 2 is 20 k
W
. Recommended input signal
level is in the range of 10 mV
RMS
to 3 V
RMS
.
FSK Data Output
(Pin 7)
This output is an open collector stage which requires a
pull-up resistor, R
L
, to +V
S
for proper operation. It can sink
5 mA of load current. When decoding FSK signals the FSK
data output will switch to a ÒhighÓ or off state for low input
frequency, and will switch to a ÒlowÓ or on state for high
input frequency. If no input signal is present, the logic state
at pin 7 is indeterminate.
Quadrature Phase Detector Output, Q
(Pin 3)
This is the high impedance output of the quadrature phase
detector, and is internally connected to the input of lock
detector voltage comparator. In tone detection applications,
pin 3 is connected to ground through a parallel combination
of R
D
and C
D
(see Figure 1) to eliminate chatter at the lock
detector outputs. If this tone detector section is not used,
pin 3 can be left open circuited.
FSK Comparator Input
(Pin 8)
This is the high impedance input to the FSK voltage
comparator. Normally, an FSK post detection or data Þlter is
connected between this terminal and the PLL phase detector
output (pin 11). This data Þlter is formed by R
F
and C
F
of
Figure 1. The threshold voltage of the comparator is set by
the internal reference voltage, V
R
, available at pin 10.
Lock Detector Output, Q
(Pin 5)
The output at pin 5 is at a ÒhighÓ state when the PLL is out of
lock and goes to a ÒlowÓ or conducting state when the PLL is
locked. It is an open collector output and requires a pull-up
resistor, R
L
, to +V
S
for proper operation. In the ÒlowÓ state it
can sink up to 5 mA of load current.
Reference Bypass
(Pin 9)
This pin can have an optional 0.1,
m
F capacitor connected to
the ground.
Reference Voltage, V
R
(Pin 10)
This pin is internally biased at the reference voltage level,
V
R
; V
R
= +V
S
/2 Ð 650 mV. The DC voltage level at this pin
forms an internal reference for the voltage levels at pin 3, 8,
11 and 12. Pin 10 must be bypassed to ground with a 0.1
m
F
capacitor.
Lock Detector Complement, Q
(Pin 6)
The output at pin 6 is the logic complement of the lock
detector output at pin 5. This output is also an open collector
type stage which can sink 5 mA of load current in the low or
ÒonÓ state.
R
B
510K
(11)
C1
Input
Preamp
(2)
VCO
0.1
µF
Input
Signal
Quad
f-Detector
(3)
R
D
100K
to 470K
Lock
Detector
Comparator
f
(14)
C0
(13)
R0
0.1
µF
f
(12)
(10)
Internal
Reference
R
F
100K
(8)
R
L
(1)
+V
S
(7)
Loop
f-Detector
R1
CF
FSK
Comparator
FSK
Output
Q
(6)
Lock
Detector
Outputs
(5)
Q
CD
65-2211-02
Figure 1. Generalized Circuit Connection for FSK and Tone Detection
2
RC2211
PRODUCT SPECIFICATION
Loop Phase Detector Output
(Pin 11)
This terminal provides a high impedance output for the loop
phase detector. The PLL loop Þlter is formed by R1 and C1
connected to pin 11 (see Figure 1). With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to V
R
. The peak voltage swing available at
the phase detector output is equal to
±
V
R
.
2.
Internal Reference Voltage, V
R
(measured at pin 10)
æ
+V
S
ö
V
R
=
è
----------
ø
-650 mV
2
3.
Loop Lowpass Filter Time Constant,
t
t
= R
1
C
1
VCO Control Input
(Pin 12)
VCO free running frequency is determined by external
timing resistor, R0, connected from this terminal to ground.
The VCO free running frequency, F
0
is given by:
1
-
F
0
(
Hz
)
= ------------
R
0
C
0
where C
0
is the timing capacitor across pins 13 and 14. For
optimum temperature stability R
0
must be in the range of
10 k
W
to 100 k
W
(see Typical Performance Characteristics).
This terminal is a low impedance point, and is internally
biased at a DC level equal to V
R
. The maximum timing cur-
rent drawn from pin 12 must be limited to
£
3 mA for proper
operation of the circuit.
4.
Loop Dampening,
z
:
æ
C
0
ö
1
z
=
ç
-----
÷ æ
--
ö
- -
è
C
1
ø è
4
ø
5.
Loop Tracking Bandwidth,
±D
F/F
0
:
Df/F
O
= R0/R1
Tracking
Bandwidth
Df
Df
F
LL
F
1
F
0
F
2
F
LH
65-2211-03
VCO Timing Capacitor
(Pins 13 and 14)
VCO frequency is inversely proportional to the external tim-
ing capacitor, C
0
, connected across these terminals. C
0
must
be non-polarized, and in the range of 200 pF to 10
m
F.
6.
FSK Data Filter Time Constant,
t
F
:
t
F
= R
F
C
F
7.
VCO Frequency Adjustment
VCO can be Þne tuned by connecting a potentiometer, Rx, in
series with R
0
at pin 12 (see Figure 2).
Loop Phase Detector Conversion Gain, K
f
(K
f
is the
differential DC voltage across pins 10 and 11, per unit
of phase error at phase-detector input):
(
Ð2
) (
V
R
)
-
kf
(
in volts per radian
)
= ---------------------------
p
VCO Free-Running Frequency,
F
0
The RC2211 does not have a separate VCO output terminal.
Instead, the VCO outputs are internally connected to the
phase detector sections of the circuit. However, for set-up or
adjustment purposes, the VCO freerunning frequency can be
measured at pin 3 (with C
D
disconnected) with no input and
with pin 2 shorted to pin 10.
8.
VCO Conversion Gain, K
0
is the amount of change in
VCO frequency per unit of DC voltage change at pin 11:
Ð1
K0
(
in Hertz per volt
)
= --------------------
-
C
0
R
1
V
R
9.
Total Loop Gain, K
T
:
K
T
(in radians per second per volt)= 2
p
K
f
K0
=
4
------------
-
C
0
R
1
Design Equations
See Figure 1 for DeÞnitions of Components.
1.
VCO Center Frequency, F
0
:
1
F
0
(
Hz
)
= ------------
-
R
0
C
0
10. Peak Phase Detector Current, I
A
:
V
R
-
I
A
(
mA
)
= ------
25
3
PRODUCT SPECIFICATION
RC2211
Pin Assignments
+V
S
Input
Lock Detector Filter
GND
Q
Q
FSK Data Output
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Timing Capacitor
Timing Capacitor
Timing Resistor
Loop
f-Detector
Reference Voltage Output
Reference Bypass
FSK Comparator Input
65-2211-04
Absolute Maximum Ratings
Parameter
Supply Voltage
Input Signal Level
Storage Temperature Range
Operating Temperature Range
RM2211D
RV2211N
RC2211N
Junction Temperature
Lead Soldering Temperature (60 sec.)
Max. P
D
T
A
<50°C
PDIP
CerDIP
PDIP
CerDIP
-65
-55
-25
-0
Min
-20
Max
+20
3
+150
+125
+85
+70
+125
+175
+300
468
1042
Unit
V
V
RMS
°C
°C
°C
°C
°C
°C
°C
mW
mW
Thermal Characteristics
Parameter
Therm. Res
q
JC
Therm. Res.
q
JA
For T
A
> 50°C Derate at
14 Lead Plastic DIP
—
160°C/W
6.5 mW/°C
14 Lead Ceramic DIP
60°C/W
120°C/W
8.33 mW/°C
4
RC2211
PRODUCT SPECIFICATION
Electrical Characteristics
(Test Conditions +V
S
= +12V, T
A
+25°C, R0 = 30 kW, C0 = 0.033
mF.
See Figure 1 for component designations.)
RV/RM2211
Parameters
General
Supply Voltage
2
Supply Current
Oscillator
Frequency Accuracy
Frequency Stability
1
Temperature Coefficient
Power Supply Rejection
Upper Frequency Limit
Lowest Practical Operating
Frequency
1
Timing Resistor, R
0
Operating Range
Recommended Range
Loop Phase Detector
Peak Output Current
Output Offset Current
Output Impedance
Maximum Swing
Quadrature Phase Detector
Peak Output Current
3
Output Impedance
Maximum Swing
Input Preamp
Input Impedance
Input Signal Voltage
Required to Cause Limiting
3
Voltage Comparator
Input Impedance
Input Bias Current
Voltage Gain
1
Output Voltage Low
Output Leakage Current
Internal Reference
Voltage Level
Output Impedance
Notes:
1. Guaranteed by design.
2. Individual applications may need special circuitry to function at <12V.
3. Sample tested.
RC2211
Min
4.5
5.0
±1.0
±20
0.05
0.2
300
Typ
Max
20
11
Units
V
mA
%
ppm/°C
%/V
%/V
kHz
Hz
Test Conditlons
Min
4.5
Typ
Max
20
R
0
³
10 kW
Deviation from f
0
= 1/R
0
C
0
R
1
=
¥
+V
S
= 12
±1V
+V
S
= 5
±0.5V
R
0
= 8.2 kW, C
0
= 400 pF
R
0
= 2 MW, C
0
= 50
mF
100
4.0
±1.0
±20
0.05
0.2
300
9.0
±3.0
±50
0.5
0.01
0.01
5.0
15
Measured at pin 11
2000
100
5.0
15
2000
100
kW
kW
mA
mA
MW
V
mA
MW
V
P-P
kW
mV
RMS
±150 ±200 ±300
±1.0
1.0
±100 ±200 ±300
±2.0
1.0
±4.0
±5.0
150
1.0
11
20
Ref. to pin 10
Measured at pin 3
±4.0
100
±5.0
150
1.0
11
Measured at pin 2
20
2.0
10
2.0
Measured at pins 3 & 8
R
L
= 5.1 kW
I
C
= 3mA
V
0
= 12V
Measured at pin 10
4.9
55
2.0
100
70
300
0.01
5.3
100
5.7
4.75
55
2.0
100
70
300
0.01
5.3
100
5.85
MW
nA
dB
mV
mA
V
W
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
