CY7C1346H
2-Mbit (64K x 36) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 64K × 36 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 3.5 ns (166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1346H SRAM integrates 64K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1346H operates from a +3.3V core power supply
while all outputs also operate with either a +3.3V/2.5V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D,
DQ
D
BYTE
WRITE REGISTER
DQ
C
,DQP
C
BYTE
WRITE REGISTER
DQ
B,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
Q0
LOGIC
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C
,DQP
C
BYTE
WRITE DRIVER
DQ
B,
DQP
B
BYTE
WRITE DRIVER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05672 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 26, 2006
[+] Feedb
CY7C1346H
Selection Guide
166 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
3.5
240
40
Unit
ns
mA
mA
Pin Configuration
100-pin TQFP Pinout
BYTE C
BYTE D
DQP
c
DQ
c
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1346H
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
Document #: 38-05672 Rev. *B
MODE
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
NC/9M
A
A
A
A
A
A
NC/4M
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 2 of 16
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CY7C1346H
Pin Definitions
Name
A
0
, A
1
, A
I/O
Description
Input-
Address Inputs used to select one of the 64K address locations.
Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
1
, A
0
feed the 2-bit counter.
Input-
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct Byte Writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of CLK, a global
Synchronous Write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
Input-
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a Byte Write.
Input-
Clock
Clock Input.
Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
BW
A
,BW
B
BW
C
,BW
D
GW
BWE
CLK
CE
1
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when a new external address is
loaded.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE
1
and CE
2
to select/deselect the device. CE
3
is sampled only when a new external address is
loaded.
Input-
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a Read cycle when emerging from a
deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW.
When asserted, it
Synchronous automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When
Synchronous asserted LOW, A is captured in the address registers. A
1
, A
0
are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When
Synchronous asserted LOW, A is captured in the address registers. A
1
, A
0
are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “Sleep” Input, active HIGH.
This input, when HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
CE
2
CE
3
OE
ADV
ADSP
ADSC
ZZ
I/O-
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by
DQ
A,
DQ
B
DQ
C,
DQ
D,
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE.
DQP
A
,
DQP
B
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed
DQP
C
,DQP
in a tri-state condition.
V
DD
V
SS
Power Supply
Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
Document #: 38-05672 Rev. *B
Page 3 of 16
[+] Feedb
CY7C1346H
Pin Definitions
(continued)
Name
V
DDQ
V
SSQ
MODE
I/O
I/O Power
Supply
I/O Ground
Input-
Static
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order.
When tied to GND selects linear burst sequence. When tied to V
DD
or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
No Connects.
Not internally connected to the die. 4M, 9M,18M, 72M, 144M, 288M, 576M and 1G
are address expansion pins and are not internally connected to the die.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
1
, CE
2
, CE
3
are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the RAM
array. The Write signals (GW, BWE, and BW
[A:D]
) and ADV
inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW
[A:D]
signals. The CY7C1346H provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW
[A:D]
) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1346H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW
[A:D]
) are asserted active to conduct a Write to
the desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to DQ is written into the corre-
sponding address location in the memory core. If a Byte Write
is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.
Because the CY7C1346H is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Page 4 of 16
Description
NC
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1346H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[A:D]
) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE
1
is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within t
CO
if OE is active LOW. The only
exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single Read cycles are supported. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tri-state immediately.
Document #: 38-05672 Rev. *B
[+] Feedb
CY7C1346H
Burst Sequences
The CY7C1346H provides a two-bit wraparound counter, fed
by A
1
, A
0
, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A
1
, A
0
00
01
10
11
Second
Address
A
1
, A
0
01
00
11
10
Third
Address
A
1
, A
0
10
11
00
01
Fourth
Address
A
1
, A
0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A
1
, A
0
00
01
10
11
Second
Address
A
1
, A
0
01
10
11
00
Third
Address
A
1
, A
0
10
11
00
01
Fourth
Address
A
1
, A
0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
0
2t
CYC
2t
CYC
Min.
Max.
40
2t
CYC
Unit
mA
ns
ns
ns
ns
Document #: 38-05672 Rev. *B
Page 5 of 16
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