IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18 and 4,096 x 18
Integrated Device Technology, Inc.
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
256 x 18-bit organization array (IDT72205LB)
512 x 18-bit organization array (IDT72215LB)
1,024 x 18-bit organization array (IDT72225LB)
2,048 x 18-bit organization array (IDT72235LB)
4,096 x 18-bit organization array (IDT72245LB)
10 ns read/write cycle time
Empty and Full flags signal FIFO status
Easily expandable in depth and width
Asynchronous or coincident read and write clocks
Programmable Almost-Empty and Almost-Full flags with
default settings
Half-Full flag capability
Dual-Port zero fall-through time architecture
Output enable puts output data bus in high-impedance
state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
and plastic leaded chip carrier (PLCC)
Industrial temperature range (–40
°
C to +85
°
C) is available
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs
are applicable for a wide variety of data buffering needs, such
as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
These FIFOs have 18-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and an input
enable pin (
WEN
). Data is read into the synchronous FIFO on
every clock when
WEN
is asserted. The output port is controlled
by another clock pin (RCLK) and another enable pin (
REN
). The
read clock can be tied to the write clock for single clock
operation or the two clocks can run asynchronous of one
another for dual-clock operation. An Output Enable pin (
OE
) is
provided on the read port for three-state control of the output.
The synchronous FIFOs have two fixed flags, Empty (
EF
) and
Full (
FF
), and two programmable flags, Almost-Empty (
PAE
)
and Almost-Full (
PAF
). The offset loading of the programmable
flags is controlled by a simple state machine, and is initiated by
asserting the Load pin (
LD
). A Half-Full flag (
HF
) is available
when the FIFO is used in a single device configuration.
These devices are depth expandable using a Daisy-Chain
technique. The XI and
XO
pins are used to expand the FIFOs.
In depth expansion configuration,
FL
is grounded on the first
device and set to HIGH for all other devices in the Daisy Chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is
fabricated using IDT’s high-speed submicron CMOS technol-
ogy.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0-D17
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
•
•
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
•
•
FLAG
LOGIC
/(
READ POINTER
READ CONTROL
LOGIC
)
(
)/
EXPANSION LOGIC
OUTPUT REGISTER
RESET LOGIC
Q0-Q17
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
RCLK
2766 drw 01
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2000 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 2000
DSC-2766/-
1
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
PIN CONFIGURATIONS
D
15
D
16
D
17
GND
RCLK
V
CC
GND
V
CC
Q
17
Q
16
GND
Q
15
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61
10
60
1
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
49
21
48
22
47
23
46
24
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
WCLK
Q
0
Q
1
GND
Q
2
Q
3
V
CC
V
CC
/
V
CC
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
Q
6
Q
5
GND
Q
4
2766 drw 02
PLCC (J68-1, order code: J)
TOP VIEW
D
16
D
17
GND
RCLK
V
CC
GND
PIN 1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
WCLK
Q
0
Q
1
GND
Q
2
Q
3
V
CC
/
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Q
17
Q
16
GND
Q
15
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
2766 drw 03
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
2
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
PIN DESCRIPTION
Symbol
D0–D17
Name
Data Inputs
Reset
I/O
I
I
Data inputs for a 18-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the
RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an
initial WRITE after power-up.
When
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
When
WEN
is LOW and
LD
is HIGH, data is written into the FIFO on every LOW-to-HIGH
transition of WCLK. When
WEN
is HIGH, the FIFO holds the previous data. Data will not be
written into the FIFO if the
FF
is LOW.
When
REN
is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the
FIFO is not empty.
Description
RS
WCLK
Write Clock
Write Enable
I
I
WEN
RCLK
Read Clock
Read Enable
I
I
REN
OE
LD
When
REN
is LOW and
LD
is HIGH, data is read from the FIFO on every LOW-to-HIGH
transition of RCLK. When
REN
is HIGH, the output register holds the previous data. Data will
not be read from the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will
be in a high-impedance state.
Output Enable
Load
I
I
FL
WXI
RXI
FF
EF
PAE
PAF
WXO
/
HF
RXO
Q0–Q17
V
CC
GND
When
LD
is LOW, data on the inputs D0–D11 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when
WEN
is LOW. When
LD
is LOW,
data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-
HIGH transition of the RCLK, when
REN
is LOW.
First Load
I
In the single device or width expansion configuration,
FL
is grounded. In the depth expansion
configuration,
FL
is grounded on the first device (first load device) and set to HIGH for all other
devices in the Daisy Chain.
In the single device or width expansion configuration,
WXI
is grounded. In the depth
expansion configuration,
WXI
is connected to
WXO
(Write Expansion Out) of the previous device.
Write Expansion
Read Expansion
Full Flag
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Write Expansion
Out/Half-Full Flag
Read Expansion
Out
Data Outputs
Power
Ground
I
I
O
O
O
In the single device or width expansion configuration,
RXI
is grounded. In the depth expansion
configuration,
RXI
is connected to
RXO
(Read Expansion Out) of the previous device.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is HIGH, the FIFO is not full.
FF
is synchronized to WCLK.
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited.
When
EF
is HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
When
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the
FIFO. The default offset at reset is 31 from empty for IDT72205LB, 63 from empty for
IDT72215LB, and 127 from empty for IDT72225LB/72235LB/72245LB.
O
When
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO.
The default offset at reset is 31 from full for IDT72205LB, 63 from full for IDT72215LB, and
127 from full for IDT72225LB/72235LB/72245LB.
In the single device or width expansion configuration, the device is more than half full
when
HF
is LOW. In the depth expansion configuration, a pulse is sent from
WXO
to
WXI
of the next device when the last location in the FIFO is written.
O
O
O
In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
of the next device
when the last location in the FIFO is read.
Data outputs for a 18-bit bus.
+5V power supply pins.
Eight ground pins for the PLCC and seven pins for the TQFP/STQFP.
3
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage
with respect to GND
Storage
Temperature
DC Output Current
Com'l & Ind'l
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage
V
CC
Com'l/Ind'l
GND
V
IH
V
IL
(1)
T
A
T
A
Supply Voltage
Input High Voltage
Com'l/Ind'l
Input Low Voltage
Com'l/Ind'l
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
4.5
0
2.0
—
0
–40
Typ.
5.0
0
—
—
—
—
Max. Unit
5.5
V
0
—
0.8
70
85
V
V
V
°C
°C
2766 tbl 03
NOTE:
2766 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V
±
10%, T
A
= –40°C to +85°C )
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
Commercial and Industrial
(1)
t
CLK
= 10, 15, 25 ns
Min.
Typ.
–1
–10
2.4
—
—
—
—
—
—
—
—
—
Symbol
I
LI
(2)
I
LO
(3)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Standby Current
Max.
1
10
—
0.4
60
5
Unit
µA
µA
V
V
mA
mA
V
OH
V
OL
I
CC1
(4,5,6)
I
CC2
(4,7)
2766 tbl 04
NOTES:
1. Industrial temperature range product for the 15ns and the 25 ns speed grade is available as a standard device.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs open (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. For the 72205/72215/72225 the typical I
CC1
= 1.81 + 1.12*f
S
+ 0.02*C
L
*f
S
(in mA);
for the 72235/72245 the typical I
CC1
= 2.85 + 1.30*f
S
+ 0.02*C
L
*f
S
(in mA).
These equations are valid under the following conditions:
V
CC
= 5V, T
A
= 25°C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
7. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
2766 tbl 05
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2766 tbl 06
NOTES:
1. With output deselected, (
OE
≥
V
IH
).
2. Characterized values, not currently tested.
4
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V
±
10%, T
A
= –40°C to +85°C)
Commercial
72205LB10
72215LB10
72225LB10
72235LB10
72245LB10
Min. Max.
—
2
10
4.5
4.5
3
0
3
0
10
8
8
—
0
3
3
—
—
—
—
—
—
3
3.5
5
5
100
6.5
—
—
—
—
—
—
—
—
—
—
15
—
6
6
6.5
6.5
17
17
17
6.5
—
—
—
—
Com'l & Ind'l
(1)
72205LB15
72205LB25
72215LB15
72215LB25
72225LB15
72225LB25
72235LB15
72235LB25
72245LB15
72245LB25
Min. Max. Min. Max.
—
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
—
—
—
—
6.5
5
6
6
66.7
10
—
—
—
—
—
—
—
—
—
—
20
—
8
8
10
10
24
24
24
10
—
—
—
—
—
2
25
10
10
6
1
6
1
25
15
15
—
0
3
3
—
—
—
—
—
—
10
10
10
10
40
15
—
—
—
—
—
—
—
—
—
—
25
—
12
12
15
15
26
26
26
15
—
—
—
—
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full
Flag
Clock to Programmable Almost-Empty
Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Set-Up Time
Skew time between Read Clock &
Write Clock for Full Flag
Skew time between Read Clock &
Write Clock for Empty Flag
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range is available as standard product for the 15ns
and the 25ns speed grade.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
2766 tbl 07
5V
1.1K
D.U.T.
680Ω
30pF*
2766 drw 04
Figure 1. Output Load
* Includes jig and scope capacitances.
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
