Si 5 3 4 5 / 4 4 /4 2
1 0 - C
H A N N E L
, A
NY
-F
R E Q U E N C Y
, A
NY
- O
U T P U T
J
I T T E R
A
T T E N U A T O R
/C
LOC K
M
U LT IP L IE R
Features
Generates any combination of output
Optional zero delay mode
frequencies from any input frequency
Fastlock feature: 50 ms typ lock time
Input frequency range:
Glitchless on the fly output frequency
Differential: 8 kHz to 750 MHz
changes
LVCMOS: 8 kHz to 250 MHz
DCO mode: as low as 0.001 ppb
Output frequency range:
steps.
Differential: up to 712.5 MHz
Core voltage
LVCMOS: up to 250 MHz
V
DD
: 1.8 V ±5%
Ultra-low jitter:
V
DDA
: 3.3 V ±5%
<100 fs typ (12 kHz–20 MHz)
Independent output supply pins: 3.3 V,
Programmable jitter attenuation
2.5 V, or 1.8 V
bandwidth from 0.1 Hz to 4 kHz
Output-output skew: <100 ps
Meets G.8262 EEC Opt 1, 2 (SyncE)
Serial interface: I
2
C or SPI
Highly configurable outputs compatible
In-circuit programmable with
with LVDS, LVPECL, LVCMOS, CML,
non-volatile OTP memory
and HCSL with programmable signal
ClockBuilder Pro
TM
software simplifies
amplitude
device configuration
Status monitoring (LOS, OOF, LOL)
Si5345: 4 input, 10 output, 64 QFN
Hitless input clock switching:
Si5344: 4 input, 4 output, 44 QFN
automatic or manual
Si5342: 4 input, 2 output, 44 QFN
Locks to gapped clock inputs
Temperature range: –40 to +85 °C
Automatic free-run and holdover
Pb-free, RoHS-6 compliant
modes
Ordering Information:
See section 8
Functional Block Diagram
XTAL
Si5345/44/42
IN_SEL
XA
XB
Device Selector Guide
Grade
Si534xA
Si534xB
Si534xC
Si534xD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Modes
Integer+Fractional
Integer+Fractional
Integer
Integer
OSC
IN0
IN1
IN2
IN3/
FB_IN
÷FRAC
÷FRAC
÷FRAC
÷FRAC
Optional
External
Feedback
DSPLL
Applications
OTN Muxponders and Transponders
10/40/100G networking line cards
GbE/10GbE/100GbE Synchronous
Ethernet (ITU-T G.8262)
Carrier Ethernet switches
SONET/SDH Line Cards
Broadcast video
Test and measurement
ITU-T G.8262 (SyncE) Compliant
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
Si5342
Si5344
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Description
These jitter attenuating clock multipliers combine fourth-generation DSPLL and
MultiSynth™ technologies to enable any-frequency clock generation and jitter
attenuation for applications requiring the highest level of jitter performance. These
devices are programmable via a serial interface with in-circuit programmable non-
volatile memory (NVM) so they always power up with a known frequency configuration.
They support free-run, synchronous, and holdover modes of operation, and offer both
automatic and manual input clock switching. The loop filter is fully integrated on-chip,
eliminating the risk of noise coupling associated with discrete solutions. Further, the
jitter attenuation bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Programming the Si5345/44/42 is easy with
Silicon Labs’
ClockBuilderPro
software. Factory preprogrammed devices are also
available.
NVM
I
2
C/SPI
Control/
Status
÷INT
÷INT
÷INT
÷INT
Si5345
Preliminary Rev. 0.95 3/15
Copyright © 2015 by Silicon Laboratories
Si5345/44/42
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5345/44/42
T
ABLE
O
F
C
ON TENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for
Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
9.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . 55
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2
Preliminary Rev. 0.95
Si5345/44/42
1. Typical Application Schematic
100 MHz (HCSL)
PCIe 3.0
CPU/NPU
133.333 MHz (CMOS)
Si5345
DSPLL
100 MHz
83.333 MHZ (CMOS)
50 MHz (CMOS)
156.25 MHz (LVDS)
125 MHz
FPGA/ASIC/
SWITCH
MultiSynth
19.44 MHz
156.25 MHz (LVDS)
MultiSynth
MultiSynth
MultiSynth
MultiSynth
155.52 MHz (LVDS)
156.525 MHz (LVDS)
2.048 MHz
10G PHY
10G PHY
125 MHz (LVPECL)
1G PHY
1G PHY
125 MHz (LVPECL)
Figure 1. 10G Ethernet Data Center Switch and Compute Blade Schematic
Preliminary Rev. 0.95
3
Si5345/44/42
2. Electrical Specifications
Table 1. Recommended Operating Conditions*
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%,T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Junction Temperature
Core Supply Voltage
Symbol
T
A
TJ
MAX
V
DD
V
DDA
Min
–40
—
1.71
3.14
3.14
2.38
1.71
Typ
25
—
1.80
3.30
3.30
2.50
1.80
3.30
1.80
Max
85
125
1.89
3.47
3.47
2.62
1.89
3.47
1.89
Unit
°C
°C
V
V
V
V
V
V
V
Clock Output Driver Supply Voltage
V
DDO
Status Pin Supply Voltage
V
DDS
3.14
1.71
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
4
Preliminary Rev. 0.95
Si5345/44/42
Table 2. DC Characteristics
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%, V
DDO
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Symbol
I
DD
I
DDA
Test Condition
Si5345,
Si5344,
Si5342
Notes
1
,
2
,
3
Min
—
—
—
—
—
—
—
—
—
—
Typ
125
120
21
15
21
16
12
880
720
715
Max
185
125
25
17
25
18
13
1040
850
840
Units
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
Output Buffer Supply Current
I
DDOx
LVPECL Output
4
@ 156.25 MHz
LVDS Output
4
@ 156.25 MHz
3.3 V LVCMOS
5
output
@ 156.25 MHz
2.5 V LVCMOS
5
output
@ 156.25 MHz
1.8 V LVCMOS
5
output
@ 156.25 MHz
Total Power Dissipation
P
d
Si5345
Si5344
Si5342
Note
1
,
6
Note
2
,
6
Note
3
,
6
Notes:
1.
Si5345 test configuration: 10x 3.3 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2.
Si5344 test configuration: 4x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3.
Si5342 test configuration: 2x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
4.
Differential outputs terminated into an AC coupled 100
load.
5.
LVCMOS outputs measured into a 6 inch 50
PCB trace with 5 pF load. Measurements were made in CMOS3 mode.
Differential Output Test Configuration
I
DDO
OUT
OUT
50
0.1 uF
50
100
0.1 uF
I
DDO
OUTa
OUTb
LVCMOS Output Test Configuration
6 inch
50
5 pF
6.
Detailed power consumption for any configuration can be estimated using
ClockBuilderPro
when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Preliminary Rev. 0.95
5
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