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SIT3808AC-DF-25SG-80.000000

产品描述Oscillator, 1MHz Min, 80MHz Max, 80MHz Nom, CMOS
产品类别无源元件    振荡器   
文件大小300KB,共5页
制造商SiTime
标准
下载文档 详细参数 全文预览

SIT3808AC-DF-25SG-80.000000概述

Oscillator, 1MHz Min, 80MHz Max, 80MHz Nom, CMOS

SIT3808AC-DF-25SG-80.000000规格参数

参数名称属性值
是否Rohs认证符合
厂商名称SiTime
包装说明DILCC6,.2
Reach Compliance Codeunknown
JESD-609代码e4
安装特点SURFACE MOUNT
端子数量6
最大工作频率80 MHz
最小工作频率1 MHz
标称工作频率80 MHz
最高工作温度70 °C
最低工作温度-20 °C
封装主体材料PLASTIC/EPOXY
封装等效代码DILCC6,.2
电源2.5 V
认证状态Not Qualified
最大压摆率33 mA
标称供电电压2.5 V
表面贴装YES
技术CMOS
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
Base Number Matches1

文档预览

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SiT3808
High Performance MEMS VCXO
Advanced information
Features, Benefits and Applications
Any frequency between 1 MHz and 80 MHz with 6 decimal places of accuracy
100% pin-to-pin compatible with and direct replacement of quartz based VCXO
Widest pull range options: ±25, ±50, ±100, ±150, ±200, ±400, ±800, ±1600 PPM
Superior pull range linearity of <= 1%, 10 times better than quartz
LVCMOS/LVTTL compatible output
Typical tuning voltage: 0 V to Vdd
Three industry-standard packages: 3.2 mm x2.5 mm (4-pin), 5.0 mm x 3.2 mm (6-pin),
7.0 mm x 5.0 mm (6-pin)
Outstanding siicon reliability of 2 FIT (10x improvement over quartz-based devices)
Ultra short lead time
Ideal for telecom clock synchronization, instrumentation, low bandwidth analog PLL,
jitter cleaner, clock recovery, audio, video, FPGA, broadband and networking
Specifications
Electrical Characteristics
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-10
-25
-50
Operating Temperature Range
Supply Voltage
T_use
Vdd
-20
-40
1.71
2.25
2.52
2.97
Typ.
Max.
80
+10
+25
+50
Unit
MHz
PPM
PPM
PPM
°C
°C
V
V
V
V
PPM
V
V
V
V
V
%
kHz
V
mA
mA
μA
%
ns
%Vdd
%Vdd
pF
ms
ms
ms
ps
ps
PPM
Condition
Inclusive of initial tolerance (F_init), operating temperature, rated
power, supply voltage change, load change
Select stability option in part number ordering (see back page)
Extended Commercial
Industrial
Pull Range
[1,2]
Upper Control Voltage
PR
VC_U
1.62
2.25
2.52
3
+70
+85
1.8
1.89
2.5
2.75
2.8
3.08
3.3
3.63
±25, ±50, ±100,±150,
Positive slope
8
3.3
29
31
1.0
6
1.7
0.51
1.7
2.3
2.6
3.1
0.1
1
3.63
33
31
TBD
55
2.2
10
15
10
TBD
10
±200, ±400, ±800, ±1600
Vdd = 1.8 V, Voltage at which maximum deviation is guaranteed.
Vdd = 2.5 V, Voltage at which maximum deviation is guaranteed.
Vdd = 2.8 V, Voltage at which maximum deviation is guaranteed.
Vdd = 3.3 V, Voltage at which maximum deviation is guaranteed.
Voltage at which maximum deviation is guaranteed.
Lower Control Voltage
Linearity
Frequency Change Polarity
Control Voltage Bandwidth(-3dB)
Current Consumption
Standby Current
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Output Load
Start-up Time
OE Enable/Disable Time
Resume Time
RMS Period Jitter
RMS Phase Jitter (random)
Aging
VC_L
Lin
V_BW
Idd
I_std
DC
Tr, Tf
VOH
VOL
Ld
T_start
T_oe
T_resume
T_jitt
T_phj
F_aging
0
2.97
45
90
Contact SiTime for 16 kHz bandwidth
No load condition, f = 20 MHz, Vdd = 2.5 V, 2.8 V or 3.3 V
No load condition, f = 20 MHz, Vdd = 1.8 V
ST = GND, All Vdd, Output is Weakly Pulled Down
All Vdds
Vdd = 1.8, 2.5, 2.8 or 3.3 V, 10% - 90% Vdd level
IOH = TBD
IOL = TBD
±5
Measured from the time ST pin crosses 50% threshold
f = 10 MHz, all Vdds
f = 10 MHz, Pull range = 100 PPM, Integration bandwidth = 12kHz
to 20MHz, all Vdds
10 years
Notes:
1. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.
2. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)
SiTime Corporation
Rev. 0.56
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised July 13, 2011
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