DS-11802
FOUR QUADRANT MULTIPLYING SIN/COS DAC,
MICROPROCESSOR COMPATIBLE, 16-BIT HYBRID
DESCRIPTION
The DS-11802 is a small size, high
accuracy, 16-bit digital-to-sine/cosine
converter. Available in accuracies up
to 1 arc minute, the DS-11802 is con-
tained in a 28-pin DDIP and requires
+15 Vdc and -15 Vdc power supplies.
The reference input is buffered
through an op-amp to minimize load-
ing on the input signal and can accept
up to ±10 V peak. The DS-11802 is
pin programmable for gains of 0.5,
1.0, and 2.0. Two registers for the
input of the 16-bit (CMOS/TTL) natur-
al binary angle data allow for compat-
ibility with an 8-bit or 16-bit data bus.
Internally, the DS-11802 has a multi-
plying digital-to-sin/cos converter
consisting of two function generators
and a quadrant select network.
Quadrant information is available
from the two most significant bits
(MSBs). The two function generators
use the remaining angular data along
with the buffered reference voltage.
Similar to a multiplying DAC (digital-
to-analog converter), the DS-11802
uses high-accuracy resistive ladder
networks and solid-state switching to
control the attenuation of the refer-
ence voltage. The output buffer ampli-
fiers allow for up to 2 mA output drive.
FEATURES
•
28-Pin Ceramic DDIP Package
•
1 Arc Minute Accuracy
•
0.03% Radius Accuracy
•
Microprocessor Compatible -
8- and 16-Bit
APPLICATIONS
Due to the high accuracy, high reliabil-
ity, small size, low power consumption
and MIL-PRF-38534 processing avail-
able, the DS-11802 is suitable for
industrial and military ground or avion-
ic applications. Possible applications
include digital remote positioning,
resolver angle simulation, flight train-
ers, flight instrumentation, radar and
navigational systems, and PPI dis-
plays including moving target indica-
tors. Other applications are syn-
chro/resolver system development
and testing, and wraparound test of
synchro/resolver-to-digital converters.
•
Double-Buffered Inputs
•
Pin-Programmable Gain -
0.5, 1.0 or 2.0
•
Buffered Reference Input
•
DC-Coupled Reference and
Outputs
•
Requires Only ±15 V Power
Supplies
•
TTL and CMOS Compatible
•
Pin-for-Pin Replacement for
Natel’s HDSC2306
26
+V –V
S
S
27
HBE 9
(MSB) B1 1
B2 2
B3 3
B4 4
B5 5
B6 6
INPUT BUFFERS
B7 7
B8 8
16-BIT
HOLDING
REGISTER
16-BIT
HIGH
ACCURACY
MULTIPLYING
DIGITAL
TO SIN / COS
CONVERTER
CK
Q1
8-BIT
INPUT
REGISTER
D
BIT 1
(MSB)
28 SINθ
B9 11
B10 12
B11 13
B12 14
B13 15
B14 16
B15 17
(LSB) B16 18
BUFFER
AMPLIFIERS
21 COSθ
8-BIT
INPUT
REGISTER
D
Q16
CK
CK
BIT16
(LSB)
LBE 10
LDC 19
REFERENCE
CONDITIONER
25
GND
20
VIN
22
23
TP1 GC1
24
GC2
FIGURE 1. DS-11802 BLOCK DIAGRAM
©
1996, 1999 Data Device Corporation
TABLE 1. DS-11802 SPECIFICATIONS
PARAMETER
VALUE
REMARKS
DIGITAL ANGULAR
Resolution
16 Bits
Bit 1 = MSB, Bit 16 = LSB
Accuracy
±4 arc-minutes
Accuracy applies over
±2 arc-minutes
operating temperature
±1 arc-minutes
range.
ANALOG INPUT
(V
IN
)
Voltage
Frequency Range
Input Resistance
ANALOG OUTPUTS
SIN
θ
COS
θ
TABLE 1. DS-11802 SPECIFICATIONS (CONTINUED)
PARAMETER
VALUE
REMARKS
REGISTER CONTROLS
(Continued)
200
ηsec
min
Before data transfer.
Data Set-up Time
Data Hold Time
Before input data
200
ηsec
min
changes.
POWER SUPPLIES
Supply Voltages (±Vs)
Supply Current
Supply Rejection
±15 V dc ±10%
±25 mA max
80 db typ
For ±10 V pk output.
0 to ±10 Vp ac or dc
dc to 1000 Hz
1 MΩ min
K • V
in
•
SIN
θ
K • V
in
•
COS
θ
0.5 ±0.2%
1.0 ±0.2%
2.0 ±0.2%
±0.1%
2 mA rms
<
1 ohm
±10 mV typical
±25 mV max
25
µV/°C
30
µsec
max to
accuracy of con-
verter
Op amp buffer
±10 Vp AC or DC
±10 Vp AC or DC
Pin 23 connected to gnd.
Pin 24 no connection.
Pin 24 connected to gnd.
Pin 23 no connection.
Pin 23 and 24 floating.
Guaranteed, but not
tested.
Op amp output.
Converter Gain (K)
TEMPEATURE RANGES
Operating Case
-3XX and -8XX
-5XX and -2XX
-1XX and -4XX
Storage
PHYSICAL
CHARACTERISTICS
Type
Size
Weight
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
-65°C to +135°C
Radius Accuracy
Output Current
Output Impedance
Zero Offset (dc)
Offset Drift
Output Settling Time
28 Pin Double DIP
0.6 x 1.4 x 0.2 in.
(15 x 36 x 5) mm
0.5 oz
(15 gm) max
-Vs to +Vs
±18 V dc
-0.3 V dc to +6.5 V dc
For any digital step
change.
ABSOLUTE MAXIMUM RATINGS
Reference Input:
Power Supply Voltage (±Vs):
Digital Inputs:
DIGITAL INPUTS
Logic Voltage Levels
Logic 0
Logic 1
Loading
Input Current
Data Bits (B1-B16)
No external logic volt-
ages required.
-0.3 V DC to 0.8 V DC
2.4 V DC to 5.5 V DC
0.1 TTL load
CMOS transient pro-
tected.
15
µA
typ, “active” For less than 16 bits,
unused pins can be
pull-down to gnd
left unconnected.
-15
µA
typ, “active”
pull-up to internal Pins not used can be
left unconnected.
logic supply
ANALOG OUTPUT GAIN CONTROL AND PHASING
The DS-11802 is pin-programmable for gains of 0.5, 1.0 and 2.0.
TABLE 2 details the programming of gain control pins 23 (GC1)
and 24 (GC2). When both pins are left unconnected or open, the
gain of the converter is 2.0. The output signal would be: 2 Vin
sinθ and 2 Vin cosθ. When GC2 is connected to GND and GC1
is left open, the converter gain is 1.0. When GC1 is connected
to GND and GC2 is left open, the converter gain is 0.5. When
looking at the equivalent gain circuit (see FIGURE 2) the gain of
the converter can be modified by adding a resistor between GC1
or GC2 and GND.
HBE, LBE, LDC
REGISTER CONTROLS
HBE
(High Byte Enable)
Logic 1
Logic 0
8 MSBs enter high
byte input register.
High byte register
remains unaffected.
8 LSBs enter low byte
input register.
Low byte register
remains unaffected.
Data from input regis-
ters transferred to
holding register.
Data in holding regis-
ter remains unaffected.
GC1
(PIN 23)
Gnd
Open
Open
TABLE 2. GAIN CONTROL PINS
GC2
(PIN 24)
Open
Gnd
Open
GAIN
(K)
0.5
1.0
2.0
LBE
(Low Byte Enable)
Logic 1
Logic 0
LDC
(Load Converter)
Logic 1
Logic 0
Users are cautioned against using a large value resistor to
modify the gain, as the temperature coefficient of the exter-
nal resistor will not be matched with the TCR of the internal
resistor.
The internal gain resistors have an accuracy of 0.05%.
FIGURE 3 illustrates the output phasing between the reference
voltage Vin and the analog output signals as a function of the
digital angle and the converter gain K (0.5, 1.0, or 2.0).
2
DIGITAL INTERFACE
The DS-11802 has double-buffered input registers which allow
easy implementation of an interface with 8-bit or 16-bit data
buses. The DS-11802 can also be set up for asynchronous data
inputs. If the LBE, HBE and LDC input pins are left open, the
internal pull-up circuitry will set these pins to a high state and the
information at the data inputs (B1-B16) is continuously convert-
ed to sinθ and cosθ at the analog outputs. For applications
requiring less than 16-bit resolution, the unused data bit pins can
be left open. The data bits (B1-B16) are internally pulled-down to
apply a logic “0” to unconnected data inputs.
DATA TRANSFER FROM AN 8-BIT DATA BUS
Applications with a 8-bit data bus require two-byte loading of the
digital input (see FIGURE 4).
FIGURE 5 shows the timing for two-byte data transfers.
1
TP1
20
22
2
3
LBE
HBE
LDC
LOAD LSBs
LOAD MSBs
LOAD
CONVERTER
V
IN
21K
2.33K
4
10
9
19
INTERNAL
REFERENCE
DATA BUS
5
6
7
GC1 23
GC2 24
2.92K
(MSB)
D7
D6
D5
D4
D3
D2
D1
D0
HBE
LBE
8
DS-11802
11
12
13
14
15
16
17
18
8.75K
(LSB)
FIGURE 2. REFERENCE CONDITIONER
SIN
θ
FIGURE 4. DATA TRANSFER FROM 8-BIT BUS
+V
MAX
8 LSBs TRANSFERRED
TO INPUT REGISTERS
DATA
CHANGING
DATA
STEADY
(LSBs)
(MSBs)
In Phase with V
in
0
90
180
270
360
θ
(DEGREES)
DATA
DATA SET UP
Data Hold
200 ns
MIN
8 MSBs TRANSFERRED
TO INPUT REGISTERS
-V
MAX
COS
θ
LBE
PULSE
WIDTH
800 ns
MIN
DATA HOLD
200ns
MIN
PULSE
WIDTH
800 ns
MIN
SIN OUTPUT = K • Vin
•
(1+n) SIN
θ
COS OUTPUT = K • Vin
•
(1+n) COS
θ
WHERE:
K IS THE GAIN OF THE CONVERTER.
n IS THE SCALE FACTOR VARIATION AS A
FUNCTION OF DIGITAL ANGLE(±
0.2%)
HBE
600ns
MIN
PULSE
WIDTH
DATA TRANSFERRED TO
HOLDING REGISTERS
LDC
FIGURE 3. OUTPUT PHASING
3
FIGURE 5. TIMING FOR 8-BIT BUS TRANSFER
1. The LDC is low (logic 0) so that the contents of the holding reg-
ister are latched and will remain unaffected by the changes on
the input registers.
2. When the LBE is set high (logic 1) the 8 LSBs (B9-B16) are
transferred to the low byte. The LBE must remain high for a min-
imum of 800 nsec after the data is stable. The data should
remain stable for 200 nsec after the LBE is set low (logic 0).
3. When the HBE is set high (logic 1) the 8 MSBs (B1-B8) are
transferred to the low byte. The HBE must remain high for a min-
imum of 800 nsec after the data is stable. The data should
remain stable for 200 nsec after the HBE is set low (logic 0).
4. When the LDC is set high (logic 1) the data is transferred from
the two input registers to the holding register. The LDC should
be held high for 600 nsec minimum. Once the LDC is set low,
the cycle can begin again.
Note: LBE, HBE, and LDC are level-actuated functions. Refer to
TABLE 3 for bit values.
DIGITAL-TO-RESOLVER/SYNCHRO CONVERTERS
The output of the DS-11802 is a single-ended sin/cos.
FIGURE 8 illustrates a schematic for a 4-Wire Digital-to-Resolver
Converter (S1, S2, S3, and S4) using external power amplifiers
and transformers.
FIGURE 9 illustrates a schematic for 3-Wire Digital-to-Synchro
Converter (S1, S2, and S3) using an additional power stage and
external transformers.
A benefit to the designs shown in FIGURES 8 and 9 is the abili-
ty to keep the converters near the digital data and control sig-
nals, and to mount the power amplifiers and transformers in a
better thermal location. This would isolate heat dissipating cir-
cuits from high-accuracy computing circuits.
(MSB)
B1
B2
B3
1
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
LDC
LOAD
CONVERTER
10
9
LBE
HBE
NOT CONNECTED
OR LOAD DATA PULSE
TABLE 3. DIGITAL ANGLE INPUTS
BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DEG/BIT
180.0
90.0
45.0
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10800.0
5400.0
2700.0
1350.0
675.0
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
(LSB)
DS-11802
FIGURE 6. DATA TRANSFER FROM 16-BIT BUS
Note:
HBE
enables the MSBs and
LBE
enables the LSBs.
DATA
CHANGING
DATA
DATA
STEADY
ALL 16 BITS
DATA TRANSFERRED
TO INPUT REGISTERS
200 ns
MIN
200 ns
MIN
DATA TRANSFER FROM A 16-BIT DATA BUS
Applications interfacing with a 16-bit data bus require only single
byte loading (see FIGURE 6). LBE and HBE are either uncon-
nected or tied together and pulsed high to load data.
As shown in the timing diagram (see FIGURE 7) 200 nsec after
the data has been stable, the LDC is set high (logic 1) to trans-
fer the data to the holding register. Since LDC is level actuated,
it must remain high for the time specified (600 nsec).
HBE LBE
800 ns
MIN
DATA TRANSFERRED TO
HOLDING REGISTERS
600 ns
MIN
LDC
FIGURE 7. TIMING FOR 16-BIT BUS TRANSFER
4
LOW FREQUENCY SINE WAVE OSCILLATOR
The DS-11802 can be used to create a low frequency sine wave
oscillator with very low distortion (see FIGURE 10). The output
amplitude is determined by the amplitude of the dc reference
input and the gain control pin configuration. When using a 16-bit
counter and a square wave of 65,536 Hz (2N, where N = 16 bit
resolution) the output will be at 1 Hz.
POWER SUPPLY DECOUPLING
Decoupling capacitors are recommended on the
+Vs
and
-Vs
.
supplies. A 1
µ
F tantalum capacitor in parallel with a 0.01
µ
F
ceramic capacitor should be mounted as close to the supply as
possible.
RH
RL
1:n
VIN
20
28
SIN
θ
P.A.
1:N
S3
S1
DS-11802
DIGITAL
ANGLE
θ
21
INTERFACE
CONTROLS
COS
θ
P.A.
1:N
S2
S4
FIGURE 8. 4-WIRE DIGITAL-TO-RESOLVER CONVERTER
RH
RL
1:n
VIN
20
28
SIN
θ
1:N
P.A.
S1
S3
DS-11802
DIGITAL
ANGLE
θ
21
INTERFACE
CONTROLS
COS
θ
P.A.
1:
√
3 N
2
S2
FIGURE 9. 3-WIRE DIGITAL-TO-SYNCHRO CONVERTER
SQUARE WAVE
OSCILLATOR
DC REFERENCE
(Vref)
REFERENCE
INPUT
K
·
Vref
·
SIN
θ
SINE WAVE OUTPUT
16-BIT
COUNTER
DIGITAL
INPUT
DS-11802
K
·
Vref
·
COS
θ
QUADRATURE OUTPUT
FIGURE 10. LOW FREQUENCY SINEWAVE OSCILLATOR
5
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