18Mb Pipelined
QDR™II SRAM
Burst of 4
Features
•
•
•
•
•
•
•
•
•
18Mb Density (1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
Dual Echo Clock Output
4-Word Burst on all SRAM accesses
Multiplexed Address Bus One Read or One Write request per
clock cycle
DDR (Double Data Rate) Data Bus
- Four word burst data per two clock cycles on each port
- Four word transfers per clock cycle
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals from
1.4V to 1.9V.
Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level from 1.4V
to 1.9V.
- Output Impedance adjustable from 35Ω to 70Ω
1.8V Core Voltage (V
DD
)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
IDT71P74804
IDT71P74604
Description
The IDT QDRII
TM
Burst of four SRAMs are high-speed synchro-
nous memories with independent, double-data-rate (DDR), read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput, with four data items passed
with each read or write. Four data word transfers occur per clock
cycle, providing quad-data-rate (QDR) performance. Comparing this
with standard SRAM common I/O (CIO), single data rate (SDR) de-
vices, a four to one increase in data access is achieved at equivalent
clock speeds. Considering that QDRII allows clock speeds in excess of
standard SRAM devices, the throughput can be increased well beyond
four to one in most applications.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
The QDRII has a single SDR address bus with read addresses
and write addresses multiplexed. The read and write addresses inter-
leave with each occurring a maximum of every other cycle. In the event
that no operation takes place on a cycle, the subsequest cycle may
begin with either a read or write. During write operations, the writing of
individual bytes may be blocked through the use of byte write control
signals.
•
•
•
Functional Block Diagram
D
(Note1)
DATA
REG
WRITE DRIVER
OUTPUT SELECT
SENSE AMPS
(Note 4)
OUTPUT REG
SA
(Note 4)
OUTPUT SELECT
(Note2)
WRITE/READ DECODE
ADD
(Note2)
REG
R
W
BWx
(Note3)
CTRL
LOGIC
18M
MEMORY
ARRAY
(Note1)
Q
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
CQ
CQ
Notes
1) Represents
2) Represents
3) Represents
4) Represents
6111 drw16
18 data signal lines for x18 and 36 signal lines for x36.
18 address signal lines for x18 and 17 address signal lines for x36.
2 signal lines for x18 and 4 signal lines for x36.
36 signal lines for x18 and 72 signal lines for x36.
SEPTEMBER 2008
1
©2008 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6111/02
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
The QDRII has echo clocks, which provide the user with a clock
that is precisely timed to the data output, and tuned with matching imped-
ance and signal quality. The user can use the echo clock for down-
stream clocking of the data. Echo clocks eliminate the need for the user
to produce alternate clocks with precise timing, positioning, and signal
qualities to guarantee data capture. Since the echo clocks are gener-
ated by the same source that drives the data output, the relationship to
the data is not significantly affected by voltage, temperature and process,
as would be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a V
DDQ
and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V V
DD
.
The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in four word bursts, with
addressing capability to the burst level.
Clocking
The QDRII SRAM has two sets of input clocks, namely the K,
K
clocks and the C,
C
clocks. In addition, the QDRII has an output “echo”
clock, CQ,
CQ.
The K and
K
clocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R,
W
and
BWx),
the address, first
and third words of the data burst during a write operation. The
K
clock
is used to clock in the control signals (BWx) and the second and fourth
words of the data burst during a write operation. The K and
K
clocks are
also used internally by the SRAM. In the event that the user disables the
C and
C
clocks, the K and
K
clocks will be used to clock the data out of
the output register and generate the echo clocks.
The C and
C
clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C
must be presented to the SRAM within the timing tolerances. The
output data from the QDRII will be closely aligned to the C and
C
input,
through the use of an internal DLL. When C is presented to the QDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the
C
clock.
The C and second data word of the burst will also correspond. The third
and fourth data words will follow on the next clock cycle of
C
and C,
respectively.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and
C
may be disabled by tying both signals high, forcing the outputs and
echo clocks to be controlled instead by the K and
K
clocks.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and
C
with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding
Doff
low. With the DLL off, the C and
C
(or K and
K
if C and
C
are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and
CQ,
are generated by the C and
C
clocks
(or K,
K
if C,
C
are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of
CQ.
The rising edge of
C
generates
the rising edge of
CQ
and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
QDRII devices internally store the 4 words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte write signals can be used to prevent writing any individual bytes, or
combined to prevent writing one word of the burst.
Read and write operations may be interleaved with each occurring
on every other clock cycle. In the event that two reads or two writes are
requested on adjacent clock cycles, the operation in progress will com-
plete and the second request will be ignored. In the event that both a
read and write are requested simultaneously, the read operation will win
and the write operation will be ignored.
Read operations are initiated by holding the read port select (R) low,
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
with the C and
C
clocks.
Write operations are initiated by holding the write port select (W) low
and presenting the designated write address to the address bus. The
QDRII SRAM will receive the address on the rising edge of clock K
.
On
the following rising edge of K clock, the QDRII SRAM will receive the first
data item of the four word burst on the data bus. Along with the data, the
byte write (BWx) inputs will be accepted, indicating which bytes of the
data inputs should be written to the SRAM. On the following rising edge
of
K,
the next word of the write burst and
BWx
will be accepted. The
subsequent K and
K
rising edges will receive the last two words of the
four word burst, with their
BWx
enables.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with V
DDQ
= 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to V
DDQ
.
6.42
2
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
IDT71P74804 SRAM 18-Bit)of 4
18 Mb QDR II (1M x Burst 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Commercial Temperature Range
Pin Definitions
Symbol
D[X:0]
Pin Function
Input Synchronous
Description
Data input signals, sampled on the rising edge of K and
K
clocks during valid write operations
1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of
K
clocks
during write operations. Used to select which byte is written into the device during the current portion of the write operations.
Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written in to the device.
1M x 18 --
BW
0
controls D[8:0] and
BW
1
controls D[17:9]
512K x 36 --
BW
0
controls D[8:0],
BW
1
controls D[17:9],
BW
2
controls D[26:18] and
BW
3
controls D[35:27]
Address inputs are sampled on the rising edge of K clock during active read or write operations. These address inputs are
multiplexed so a read and write can be initiated on alternate clock cycles. These inputs are ignored when the appropriate port is
deselected.
BW
0
,
BW
1
BW
2
,
BW
3
Input Synchronous
SA
Input Synchronous
Q[X:0]
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge
Output Synchronous of both the C and
C
clocks during Read operations or K and
K
when operating in single clock mode. When the Read port is
deselected, Q[X:0] are automatically three-stated.
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation
is initiated. Deasserting will deselect the Write port, causing D[X:0] to be ignored. If a write operation has successfully been
initiated, it will continue to completion, ignoring the
W
on the following clock cycle. This allows the user to continuously hold
W
low
while bursting data into the SRAM.
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a read operation is
initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to
complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access
consists of a burst of four sequential transfer. If a read operation has successfully been initiated, it will continue to completion,
ignoring the
R
on the following clock cycle. This allows the user to continuously hold
R
low while bursting data from the SRAM.
Positive Output Clock Input. C is used in conjunction with
C
to clock out the Read data from the device. C and
C
can be used
together to deskew the flight times of various devices on the board back to the controller. See application example for further
details.
Negative Output Clock Input.
C
is used in conjunction with C to clock out the Read data from the device. C and
C
can be used
together to deskew the flight times of various devices on the board back to the controller. See application example for further
details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K
is used to capture synchronous inputs being presented to the device and to drive out data
through Q[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and
can be used as a data valid indication. These signals are free running and do not stop when the output data is three-stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
DDQ,
which enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
6111 tbl 02a
W
Input Synchronous
R
Input Synchronous
C
Input Clock
C
Input Clock
K
Input Clock
K
Input Clock
CQ,
CQ
Output Clock
ZQ
Input
6.42
3
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the
DLL turned off will be different from those listed in this data sheet. There will be an increased
propagation delay from the incidence of C and
C
to Q, or K and
K
to Q as configured. The
propagation delay is not a tested parameter, but will be similar to the propagation delay of other
SRAM devices in this speed grade.
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to V
DD
when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to V
DD
when the pin is unconnected.
No connects inside the package. Can be tied to any voltage level
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground for the device. Should be connected to ground of the system.
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for
HSTL or scaled to the desired output voltage.
6111 tbl 02b
Doff
Input
TDO
TCK
TDI
TMS
NC
V
REF
V
DD
V
SS
V
DDQ
Output
Input
Input
Input
No Connect
Input
Reference
Power
Supply
Ground
Power
Supply
6.42
4
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
IDT71P74804 SRAM 18-Bit)of 4
18 Mb QDR II (1M x Burst 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Commercial Temperature Range
Pin Configuration IDT71P74804 (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA
(3)
Q
9
NC
D
11
NC
Q
12
D
13
V
REF
NC
NC
Q
15
NC
D
17
NC
TCK
3
NC/
SA
(1)
D
9
D
10
Q
10
Q
11
D
12
Q
13
V
DDQ
D
14
Q
14
D
15
D
16
Q
16
Q
17
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS/
SA
(2)
NC
Q
7
NC
D
6
NC
NC
V
REF
Q
4
D
3
NC
Q
1
NC
D
0
TMS
11
CQ
Q
8
D
8
D
7
Q
6
Q
5
D
5
ZQ
D
4
Q
3
Q
2
D
2
D
1
Q
0
TDI
6111 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
6.42
5
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