®
HIP6521
Data Sheet
December 27, 2004
FN4837.3
PWM and Triple Linear Power Controller
The HIP6521 provides the power control and protection for
four output voltages in high-performance microprocessor
and computer applications. The IC integrates a voltage-
mode PWM controller and three linear controllers, as well as
monitoring and protection functions into a 16-lead SOIC
package. The PWM controller is intended to regulate the
microprocessor memory core voltage with a synchronous-
rectified buck converter. The linear controllers are intended
to regulate the computer system’s AGP 1.5V bus power, the
2.5V clock power, and the 1.8V power for the North/South
Bridge core voltage and/or cache memory circuits. Both the
switching regulator and linear voltage references provide
±2%
of static regulation over line, load, and temperature
ranges. All outputs are user-adjustable by means of an
external resistor divider. All linear controllers employ bipolar
NPNs for the pass transistors.
The HIP6521 monitors all the output voltages. The PWM
controller’s adjustable overcurrent function monitors the
output current by using the voltage drop across the upper
MOSFET’s r
DS(ON)
. The linear regulator outputs are
monitored via the FB pins for undervoltage events.
Features
• Provides 4 Regulated Voltages
- Memory Core, AGP, Clock, and Memory Controller Hub
Power
• ACPI Compatible
• Drives Bipolar Linear Pass Transistors
• Externally Resistor-Adjustable Outputs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- All Outputs:
±2%
Over Temperature
• Overcurrent Fault Monitors
- Switching Regulator Does Not Require Extra Current
Sensing Element, Uses MOSFET’s r
DS(ON)
• Small Converter Size
- 300kHz Constant Frequency Operation
- Small External Component Count
•
Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER
HIP6521CB
HIP6521CBZ
(Note)
HIP6521CBZA
(Note)
HIP6521EVAL1
TEMP.
RANGE (°C)
0 to 70
0 to 70
0 to 70
PACKAGE
16 Ld SOIC
PKG.
DWG. #
M16.15
Applications
• Motherboard Power Regulation for Computers
16 Ld SOIC
(Pb-free)
M16.15
16 Ld SOIC
(Pb-free)
M16.15
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Evaluation Board
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Add “-T” suffix for tape and reel.
Pinout
HIP6521 (SOIC)
TOP VIEW
DRIVE2 1
FB2 2
FB 3
COMP 4
GND 5
PHASE 6
BOOT 7
UGATE 8
16 FB3
15 DRIVE3
14 FB4
13 DRIVE4
12 OCSET
11 VCC
10 LGATE
9 PGND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP6521
Absolute Maximum Ratings
UGATE, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V
VCC, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
DRIVE, LGATE, all other pins . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
Operating Conditions
Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
POWER-ON RESET
Rising VCC Threshold
Falling VCC Threshold
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
UGATE, LGATE, DRIVE2, DRIVE3, and
DRIVE4 Open
-
5
-
mA
4.25
3.75
-
-
4.5
4.0
V
V
OSCILLATOR AND SOFT-START
Free Running Frequency
Ramp Amplitude
Soft-Start Interval
REFERENCE VOLTAGE
Reference Voltage (All Regulators)
All Outputs Voltage Regulation
LINEAR REGULATORS (OUT2, OUT3, AND OUT4)
Output Drive Current (All Linears)
Undervoltage Level (V
FB
/V
REF
)
V
UV
VCC > 4.5V
100
-
120
70
-
-
mA
%
V
REF
-
-2.0
0.800
-
-
+2.0
V
%
F
OSC
∆V
OSC
T
SS
275
-
6.25
300
1.5
6.83
325
-
7.40
kHz
V
P-P
ms
SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
PWM CONTROLLER GATE DRIVERS
UGATE Source
UGATE Sink
LGATE Source
LGATE Sink
PROTECTION
OCSET Current Source
I
OCSET
34
40
46
µA
I
UGATE
I
UGATE
I
LGATE
I
LGATE
VCC = 5V, V
UGATE
= 2.5V
V
UGATE-PHASE
= 2.5V
VCC = 5V, V
LGATE
= 2.5V
V
LGATE
= 2.5V
-
-
-
-
-1
1
-1
2
-
-
-
-
A
A
A
A
GBWP
SR
COMP = 10pF
-
15
-
80
-
6
-
-
-
dB
MHz
V/µs
4
FN4837.3
December 27, 2004
HIP6521
Functional Pin Descriptions
VCC (Pin 11)
Provide a well decoupled 5V bias supply for the IC to this
pin. This pin also provides the gate bias charge for the lower
MOSFET controlled by the PWM section of the IC, as well as
the base current drive for the linear regulators’ external
bipolar transistors. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.
FB2, 3, 4 (Pins 2, 16, 14)
Connect the output of the corresponding linear regulators to
these pins through properly sized resistor dividers. The
voltage at these pins is regulated to 0.8V. These pins are
also monitored for undervoltage events.
Quickly pulling and holding any of these pins above 1.25V
(using diode-coupled logic devices) shuts off the respective
regulators. Releasing these pins from the pull-up voltage
initiates a soft-start sequence on the respective regulator.
GND (Pin 5)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
Description
Operation
The HIP6521 monitors and precisely controls 4 output
voltage levels (Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). It is
designed for microprocessor computer applications with
3.3V, and 5V (5V
DUAL
) bias input from an ATX power
supply. The IC has a synchronous PWM controller and
three linear controllers. The PWM controller (PWM) is
designed to regulate the 2.5V memory voltage (V
OUT1
).
The PWM controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter configuration and
regulates the output voltage to a level programmed by a
resistor divider. The linear controllers are designed to
regulate three more of the computer system’s voltages,
typically the 1.5V AGP bus (V
OUT4
), the 2.5V clock voltage
(V
OUT2
), and the 1.8V ICH/MCH core voltage (V
OUT3
). All
linear controllers are designed to employ external NPN
bipolar pass transistors.
PGND (Pin 9)
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
BOOT (Pin 7)
Connect a suitable capacitor (0.47µF recommended) from
this pin to PHASE. This bootstrap capacitor supplies UGATE
driver the energy necessary to turn and hold the upper
MOSFET on.
OCSET (Pin 12)
Connect a resistor from this pin to the drain of the upper
PWM MOSFET. This resistor, an internal 40µA current
source (typical), and the upper MOSFET’s on-resistance set
the converter overcurrent trip point. An overcurrent trip
cycles the soft-start function.
The voltage at this pin is monitored for power-on reset (POR)
purposes and pulling this pin below 1.25V with an open
drain/collector device will shutdown the switching controller.
Initialization
The HIP6521 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage. The POR monitors
the bias voltage at the VCC pin. The POR function initiates
soft-start operation after the bias supply voltage exceeds its
POR threshold.
PHASE (Pin 6)
Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin is used to monitor the voltage
drop across the upper MOSFET for overcurrent protection.
UGATE (Pin 8)
Connect UGATE pin to the PWM converter’s upper MOSFET
gate. This pin provides the gate drive for the upper MOSFET.
Soft-Start
The POR function initiates the soft-start sequence. The
PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s).
Similarly, all linear regulators’ reference inputs are clamped
to a voltage proportional to the soft-start voltage. The ramp-
up of the internal soft-start function provides a controlled
output voltage rise.
Figure 1 shows the soft-start sequence for the typical
application. At T0 the +5V
SB
bias voltage starts to ramp up
(closely followed by the +5V
DUAL
voltage) crossing the 4.5V
POR threshold at time T1. On the PWM section, the oscillator’s
triangular waveform is compared to the clamped error amplifier
LGATE (Pin 10)
Connect LGATE to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.
COMP and FB (Pins 4, 3)
COMP and FB are the available external pins of the PWM
converter error amplifier. The FB pin is the inverting input of the
error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM converter.
DRIVE2, 3, 4 (Pins 1, 15, 13)
Connect these pins to the base terminals of external bipolar
NPN transistors. These pins provide the base current drive
for the regulator pass transistors.
5
FN4837.3
December 27, 2004
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
