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Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
FEATURES
•
High speed parallel latches
•
Live insertion/extraction permitted
•
Extra data width for wide address/data paths or buses carrying
•
Power-up 3-State
•
Power-up reset
•
Ideal where high speed, light loading, or increased fan-in are
•
Output capability: +64 mA / –32 mA
•
Latch-up protection exceeds 500 mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
required with MOS microprocessors
parity
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is HIGH. This allows asynchronous operation,
as the output transition follows the data in transition. On the nLE
HIGH-to-LOW transition, the data that meets the set-up and hold
time is latched.
Data appears on the bus when the Output Enable (nOE) is LOW.
When nOE is HIGH the output is in the high-impedance state.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
PARAMETER
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Quiescent supply current
CONDITIONS
T
amb
= 25
°C;
GND = 0 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
V
O
= 0 V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5 V
Outputs LOW; V
CC
= 5.5 V
TYPICAL
3.1
2.2
4
7
500
10
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
T
amb
= –40
°
C to +85
°
C
Type number
Package
Name
74ABT16841ADL
74ABT16841ADGG
SSOP56
TSSOP56
Description
plastic shrink small outline package; 56 leads; body width 7.5 mm
plastic thin shrink small outline package; 56 leads; body width 6.1 mm
Version
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1D0 – 1D9
2D0 – 2D9
1Q0 – 1Q9
2Q0 – 2Q9
1OE, 2OE
1LE, 2LE
GND
V
CC
Data inputs
Data outputs
Output enable inputs (active-LOW)
Latch enable inputs (active rising edge)
Ground (0 V)
Positive supply voltage
FUNCTION
2004 Feb 02
2
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
PIN CONFIGURATION
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
V
CC
2Q6
2Q7
GND
2Q8
2Q9
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1LE
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1D0
1D1
1D2
1D3
1D4
1D6
1D5
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
V
CC
2D6
2D7
GND
2D8
2D9
2LE
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
3D
4
∇
EN2
C1
EN4
C3
1D
2
∇
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
SH00081
FUNCTION TABLE
INPUTS
nOE
nLE
H
H
↓
↓
X
nDx
L
H
l
h
X
OUTPUTS
nQ0 – nQ9
L
H
L
H
Z
OPERATING MODE
SA00076
LOGIC SYMBOL
55
54
52
51
49
48
47
45
44
43
L
L
L
L
H
Transparent
Latched
High impedance
1D0 1D1 1D2 1D3 1D4 1D5 1D6
56
1
1LE
1OE
1D7 1D8
1D9
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2
42
3
41
5
40
6
38
8
37
9
36
10
34
12
33
13
31
14
30
2D0 2D1 2D2 2D3 2D4 2D5 2D6
29
28
2LE
2OE
2D7 2D8
2D9
L
L
X
NC
Hold
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
↓
= HIGH-to-LOW LE transition
NC= No change
X = Don’t care
Z = High impedance “off” state
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
2004 Feb 02
3
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00024
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in HIGH state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0 V
Output in Off or HIGH state
Output in LOW state
V
I
< 0 V
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
Input transition rise or fall rate
Operating free-air temperature range
PARAMETER
Min
4.5
0
2.0
–
–
–
0
–40
Max
5.5
V
CC
–
0.8
–32
64
5
+85
V
V
V
V
mA
mA
ns/V
°C
UNIT
2004 Feb 02
4
嵌入式系统
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