Si85xx
Si85
XX
U
N ID I R E C TI ON A L
AC C
URRENT
S
ENSORS
Features
Single-chip ac current sensor
Low loss: <1.3 m primary series
resistance and <2 nH inductance
Leading-edge noise suppression
eliminates need for leading-edge
blanking
"Ping-Pong" output version allows
one Si85xx to replace two current
transformers in full-bridge designs
5, 10, and 20 A full-scale versions
±5% initial accuracy
50 kHz to 1 MHz input frequency
range
FAULT output to safeguard operation
Large 2 V
PP
min output at full scale
Pin Assignments:
See page 24
High-side or low-side current sensing
Compact 4x4x1 mm QFN package
(1 kV
RMS
isolation)
20-Pin SOIC
VDD
MODE
R1
R2
R3
R4
OUT1
OUT2
TRST/FAULT
GND
IIN
IIN
IIN
IIN
20-pin wide-body SOIC
(5 kV
RMS
isolation)
–40 to 125 °C operating range
UL/VDE/CSA approval
Si851x
IIN
IOUT
IOUT
IOUT
IOUT
IOUT
Applications
Power supplies
Motor controls
Lighting equipment
Industrial equipment
12-Pin QFN
MODE
R1
R2
R3
R4
OUT1
OUT2
TRST/FAULT
GND
IOUT
IIN
VDD
Description
The Si85xx products are unidirectional ac current sensors available in full-scale
ranges of 5, 10, and 20 A. Si85xx products are ideal upgrades for older current-
sensing technologies offering size, performance, and cost advantages over
current transformers, Hall effect devices, DCR circuits, and other approaches. The
Si85xx are extremely low-loss, adding less than 1.3 m of series resistance and
less than 2 nH series inductance in the sensing path at 25 °C. Current-sensing
terminals are isolated from the other package pins, providing up to 5 kV
RMS
isolation level per safety approval ratings.
Si851x
Safety Approval (20-Pin SOIC Only)
UL 1577 recognized
5000 V
RMS
for 1 minute
CSA component notice 5A approval
IEC 60950, 61010, 60601
approved
VDE certification conformity*
IEC 60747-5-2 (VDE0884 Part 2)
Patents pending
Functional Block Diagram
IIN
R1
R2
R3
R4
Si851x
RESET LOGIC
MODE LOGIC
MODE
R2
VDD
VIN
VDD1
TRST
IIN
GND1
Si850x
IOUT
OUT
GND2
OUT1
METAL SLUG
INTEGRATOR
SIGNAL CONDITIONING
OUT2
R1
PH1
Q1
L
C
PH2
Q2
VOUT
TEMP
SENSOR
ADC
AUTO CALIBRATION
LOGIC
Typical Application
IOUT
GND
VDD
TRST/FAULT
*Note:
Pending
Preliminary Rev. 0.21 5/09
Copyright © 2009 by Silicon Laboratories
Si85xx
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si85xx
2
Preliminary Rev. 0.21
Si85xx
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.3. Integrator Reset and Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4. Total Measurement Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.5. Effect of Temperature on Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6. Leading Edge Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7. FAULT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8. Safe Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1. Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. SOIC Layout Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3. Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4. Single-Phase Buck Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5. Full-Bridge Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6. Push-Pull Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Pin Descriptions—20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Package Outline—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Recommended PCB Landing Pattern (12-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9. Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11. Recommended PCB Landing Pattern (20-Pin SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12. Top Marking (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Preliminary Rev. 0.21
3
Si85xx
1. Electrical Specifications
Table 1. Electrical Specifications
T
A
= –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified
Parameter
Supply Voltage (V
DD
)
Supply Current
Undervoltage Lockout (V
UVLO
)
Undervoltage Lockout Hysteresis
(V
HYST
)
Logic Input HIGH Level
Logic Input LOW Level
Reset Time (t
R
)
Reset Time Resistor Range
1
R1, R2, R3, R4 Input Rise Time (t
RR
)
R1, R2, R3, R4 Input Fall Time (t
FR
)
Measurement Watchdog Timeout (t
WD
)
Series Input Resistance
Series Inductance
Input/Output Delay
1
Start-Up Self-Cal Delay (t
CAL
)
1
Input Common Mode Voltage Range
(dc)
1
Operating Input Frequency Range (f)
1
DC Power Supply Rejection Ratio
Sensitivity @ VDD = 3 V
Conditions
Min
2.7
Typ
—
4
2.3
100
—
—
—
—
—
—
50
1.3
2
150
150
—
—
—
40
404
202
101
392
196
98
Max
5.5
7
2.5
—
—
0.8
—
2500
30
30
80
—
—
200
200
—
—
1000
—
—
—
—
—
—
—
Unit
V
mA
V
mV
V
V
ns
k
ns
ns
µs
m
nH
ns
µs
V
RMS
V
RMS
kHz
db
mV/A
mV/A
mV/A
mV/A
mV/A
mV/A
Fully enabled, input frequency =
1 MHz
—
2.1
—
MODE, R1, R2, R3, R4 inputs
(TTL compatible)
Time for 5% initial accuracy
2.0
—
150
15
—
—
30
Measured from IIN to IOUT
Measured from IIN to IOUT
OUT, OUT1, OUT2 delay relative to
input
Time from VDD = V
UVLO
+ V
HYST
to
cal complete
4x4 mm QFN
SOIC-20
—
—
—
—
1000
5000
50
—
Si8501/11/17
Si8502/12/18
Si8503/13/19
—
—
—
—
—
—
Sensitivity @ VDD = 5 V
Si8501/11/17
Si8502/12/18
Si8503/13/19
Notes:
1.
Guaranteed by design and/or characterization.
2.
Maximum output load is not recommended to exceed 200 pF and 5 k.
3.
Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
4.
See "2.4. Total Measurement Error" on page 11 for more information.
4
Preliminary Rev. 0.21
Si85xx
Table 1. Electrical Specifications (Continued)
T
A
= –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified
Parameter
OUT, OUT1, OUT2 Offset Voltage
(V
OUTMIN
)
V
OUT
Slew Rate
1,2
OUT, OUT1, OUT2 Output Resistance
Total Measurement Error (%)
(–40 to 125 ºC Temp Range)
Conditions
Current flow from I
IN
to I
OUT
= 0
OUT, OUT1, OUT2 load = 5K || 50 pF
20% of full scale
3,4
(all devices)
100% of full scale
3,4
Min
—
—
20
–30
–10
Typ
50
50
—
—
—
Max
—
—
130
+30
+10
Unit
mV
V/µs
%
%
Notes:
1.
Guaranteed by design and/or characterization.
2.
Maximum output load is not recommended to exceed 200 pF and 5 k.
3.
Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
4.
See "2.4. Total Measurement Error" on page 11 for more information.
Table 2. Absolute Maximum Ratings
1
Parameter
Storage temperature
Ambient temperature under bias
Supply voltage
Voltage on any pin with respect to ground
(not including IIN, IOUT)
Output Current Drive
Lead solder temperature (10 s)
Maximum Input Current Rate of Change
Maximum Peak AC Input Current Limit
Thermal Limit (DC Current)
2
Maximum Isolation Voltage (QFN)
Maximum Isolation Voltage (SOIC-20)
ESD (CDM)
ESD (HBM)
ESD (MM)
JEDEC (JESD22-C101C)
JEDEC (JESD22-A114E)
JEDEC (JESD22-A115A)
Symbol
T
STG
T
A
V
DD
V
IN
L
O
Min
–65
–40
—
–0.5
—
—
—
—
—
—
—
–1.5
–2500
–250
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
+150
+125
5.75
VDD + 0.5
10
260
1000
200
30
1400
6000
+1.5
+2500
+ 250
Units
°C
°C
V
V
mA
ºC
A/µs
A
A
V
RMS
V
RMS
kV
V
V
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2.
Refer to “AN329: Extending the Full-Scale Range of the Si85xx” for more information.
Preliminary Rev. 0.21
5
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