电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

HV9808PJ

产品描述计数器移位寄存器 80v 32ch Hi-V out
产品类别模拟混合信号IC    驱动程序和接口   
文件大小593KB,共7页
制造商Supertex
下载文档 详细参数 全文预览

HV9808PJ概述

计数器移位寄存器 80v 32ch Hi-V out

HV9808PJ规格参数

参数名称属性值
是否Rohs认证不符合
零件包装代码LPCC
包装说明QCCJ, LDCC44,.7SQ
针数44
Reach Compliance Codecompliant
ECCN代码EAR99
数据输入模式SERIAL
显示模式DOT MATRIX
接口集成电路类型EL DISPLAY DRIVER
JESD-30 代码S-PQCC-J44
JESD-609代码e0
长度16.5862 mm
复用显示功能NO
功能数量1
区段数32
端子数量44
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC44,.7SQ
封装形状SQUARE
封装形式CHIP CARRIER
峰值回流温度(摄氏度)NOT SPECIFIED
电源5,8/80 V
认证状态Not Qualified
座面最大高度4.572 mm
最大供电电压5.5 V
最小供电电压4.5 V
标称供电电压5 V
电源电压1-最大80 V
电源电压1-分钟8 V
电源电压1-Nom60 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度16.5862 mm
最小 fmax8 MHz
Base Number Matches1

文档预览

下载PDF文档
HV9808
32-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
Processed with HVCMOS
®
technology
Output voltages up to 80V
Low power level shifting
Shift register speed 8.0MHz
Latched data outputs
5.0V CMOS compatible inputs
Forward and reverse shifting options
Diode to V
PP
allows efficient power recovery
General Description
The HV9808 is a low voltage serial to high voltage parallel
converters with push-pull outputs. This device has been designed
for use as a driver for AC-electroluminescent displays.It can also
be used in any application requiring multiple output, high voltage
current sourcing and sinking capabilities such as driving plasma
panels, vacuum fluorescent, or large matrix LCD displays. The
inputs are fully CMOS compatible.
This device consists of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. HV
OUT
1 is connected to the first stage of the shift register
through the polarity and blanking logic. Data is shifted through
the shift register on the logic low to high transition of the clock.
The HV9808 shifts data in the counter-clockwise direction when
viewed from the top of the package. A data output buffer is
provided for cascading devices.This output reflects the current
status of the last bit of the shift register (HV
OUT
32). Operation
of the shift register is not affected by the LE (latch enable), BL
(blanking), or the POL (polarity) in-puts. Transfer of data from the
shift register to the latch occurs when the LE (latch enable) input
is high. The data in the latch is stored when LE is low.
Block Diagram
VPP
Polarity
Blanking
Latch Enable
Data Input
Clock
Latch
HV
OUT
1
Latch
32-Bit
Shift
Register
HV
OUT
2
(Outputs 3 to 30
not shown)
HV
OUT
31
Latch
Data Out
Latch
HV
OUT
32

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 376  2509  2164  1161  571  22  18  46  31  49 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved