HV574
100MHz, 80-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
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HVCMOS
®
technology
5.0V CMS Logic
Output voltage up to 80V
Low power level shifting
100MHz equivalent data rate using four dynamic
shift registers
Latched data outputs
Foreward and reverse shifting options (DIR pin)
Diode to VPP allows efficient power recovery
Outputs may be hot switched
Hi-Rel processing available
General Description
The HV574 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. This device has been designed for
use as a driver for printer applications. It can also be used in any
application requiring multiple output high-voltage current sour-
cing and sinking capability such as driving plasma panels, vac-
uum fluorescent displays, or large matrix LCD displays.
The device has 4 parallel 20-bit dynamic shift registers, permitting
data rates 4X the speed of one (they are clocked together). There
are 80 static latches and control logic to perform the polarity
select and blanking of the outputs. HV
OUT
1 is connected to the first
stage of the first shift register through the polarity and blanking
logic. Data is shifted through the shift registers on the logic low
to high transition of the clock. The DIR pin causes CCW shifting
when connected to GND, and CW shifting when connected to
VDD. A data output buffer is provided for cascading devices. This
output reflects the current status of the last bit of the shift register
(HV
OUT
80). Operation of the shift register is not affected by the LE
(latch enable), BL (blanking), or the POL (polarity) inputs. Transfer
of data from the shift registers to the latches occurs when the LE
(latch enable) input is high. The data in the latches is stored when
LE is low.
Functional Block Diagram
VDD
LE
BL
POL
VPP
DIR
D
IN A
20-bit
shift
register
HV
OUT
1
D
OUT A
CLK
HV
OUT
20
HV
OUT
21
D
IN B
20-bit
shift
register
D
OUT B
HV
OUT
40
HV
OUT
41
D
IN C
D
OUT C
20-bit
shift
register
HV
OUT
60
HV
OUT
61
D
IN D
20-bit
shift
register
D
OUT D
HV
OUT
80
GND
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV574
Ordering Information
Package Options
Device
20.00x14.00mm body
3.40mm height (max)
0.65mm pitch
100-Lead PQFP
HV574
HV574PG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD
Output voltage, V
PP
Logic input levels
Ground current
1
Continuous total power dissipation
2
Operating temperature range
Storage temperature range
Lead temperature
3
Value
-0.5V to +7.5V
-0.5V to +90V
-0.3V to V
DD
+0.3V
1.5A
1200mW
-40°C to +85°C
-65°C to +150°C
260°C
Pin Configuration
100
1
100-Lead PQFP (PG)
(top view)
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect device
reliability. All voltages are referenced to device ground.
Notes:
1. Limited by the total dissipated in the package.
2. For operation above 25°C ambient derate linearly to 85
O
C at 20mW/°C.
3. 1.6mm from case for 10 seconds.
Product Marking
LLLLLL LLLL
YYWW
CCCCCCCC AAA
HV574PG
L = Lot Number
YY = Year Sealed
WW = Week Sealed
C = Country of Origin
A = Assembler ID
= “Green” Packaging
100-Lead PQFP (PG)
Recommended Operating Conditions
Sym
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
Parameter
Logic supply voltage
Output voltage
High-level input voltage
Low-level input voltage
Clock frequency per register
Operating free-air temperature
Min
4.5
12
V
DD
-0.5V
0
0.001
-40
Max
5.5
80
-
0.5
25
+85
Units
V
V
V
V
MHz
°C
Notes:
Power-up sequence should be the following:
1. Apply ground
2. Apply V
DD
3. Set all inputs (Data, CLK, Enable etc.) to a known state
4. Apply V
PP
The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV574
DC Electrical Characteristics
(Over recommended operating conditions unless otherwise noted)
Sym
I
DD
I
PP
I
DDQ
V
OH
V
OL
I
IH
I
IL
Parameter
V
DD
supply current
Quiescent V
PP
supply current
Quiescent V
DD
supply current
High-level output
Low-level output
HV
OUT
Data out
HV
OUT
Data out
Min
-
-
-
-
V
PP
-9.0
V
DD
-0.5
-
-
-
-
A
Max
30
100
100
100
-
-
3.75
0.5
1.0
-1.0
Units
mA
µA
µA
µA
V
V
V
V
µA
µA
Conditions
V
DD
= V
DD
max, f
CLK
= 25MHz
Outputs high
Outputs low
All V
IN
= V
DD
I
O
= -30mA, V
PP
= +80V
I
O
= -100µA
I
O
= +15mA, V
DD
= +5.0V
I
O
= +100µA
V
IH
= V
DD
V
IL
= 0V
High-level logic input current
Low-level logic input current
AC Electrical Characteristics
(T
Sym
f
CLK
t
WL
, t
WH
t
SU
t
H
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
*
t
WLE
t
SLE
t
r,
t
f
Parameter
Clock frequency
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
Time from latch enable to HV
OUT
= 85°C max. Logic signal inputs and data inputs have t
r
, t
f
≤ 5.0ns [10% and 90% points])
Min
0.001
0.001
20
0
15
-
-
-
25
25
0
-
Max
25
20
-
-
-
500
38
38
-
-
-
1.0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Conditions
V
DD
= 4.5V, T
J
= 25
O
C
V
DD
= 4.5V, T
J
= 125
O
C
---
---
---
C
L
= 15pF
C
L
= 15pF, V
DD
= 5.0V
C
L
= 15pF, V
DD
= 5.0V
---
---
---
C
L
= 600pF, HV
OUT
from 0 - 60V
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
LE pulse width
LE set-up time before clock rises
Output rise/fall time
* t
DLE
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR
output to stabilize).
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV574
Input and Output Equivalent Circuits
V DD
V DD
V PP
Input
Data Out
HV
OUT
GND
Logic Inputs
GND
Logic Data Output
GND
High Voltage Outputs
Switching Waveforms
V
IH
Data Input
50%
t
SU
Clock
50%
t
WL
50%
t
WH
50%
Data Out
t
DLH
50%
t
DHL
50%
t
DLE
t
WLE
50%
t
SLE
90%
10%
t
f
t
OFF
HV
OUT
w/ S/R HIGH
90%
t
r
t
ON
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
IH
V
OL
Data Valid
t
H
V
IH
50%
50%
V
IL
V
OH
V
OL
Data Valid
V
IL
Latch Enable
HV
OUT
w/ S/R LOW
10%
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV574
Function Table
Inputs
Function
All O/P high
All O/P low
O/P normal
O/P inverted
Data falls
through
(latches
transparent)
Data stored/
latches loaded
Data
X
X
X
X
L
H
L
H
X
X
D
IN
X
I/O relation
D
IN
X
D
OUT
X
D
OUT
X
CLK
X
X
X
X
↑
↑
↑
↑
X
X
↑
↑
↑
↑
LE
X
X
X
X
H
H
H
H
L
L
H
L
L
H
BL
L
L
H
H
H
H
H
H
H
H
H
H
H
H
POL
L
H
H
L
H
H
L
L
H
L
H
H
H
H
DIR
X
X
X
X
X
X
X
X
X
X
H
H
L
L
Shift Reg
-
-
-
-
L
H
L
H
*
*
Q
n
→Q
n+1
Q
n
→Q
n+1
Q
n
→Q
n-1
Q
n
→Q
n-1
Outputs
HV Outputs
H
L
No inversion
Inversion
L
H
H
L
Stored Data
Inversion of
stored data
New H or L
Previous H or L
Previous H or L
New H or L
Data Out
-
-
-
-
-
-
-
-
-
-
D
OUT
X
D
OUT
X
D
IN
X
D
IN
X
Note:
* = dependent on previous stage’s state. See Pin configuration for DIN and DOUT pin designation for CW and CCW shift.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
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