74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 03 — 23 May 2007
Product data sheet
1. General description
The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down counters. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time, or erroneous operation will result. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL).
The 74HC193 and 74HCT193 each contain four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous reset, load, and synchronous count
up and count down functions.
Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH
transition on the CPD input will decrease the count by one, while a similar transition on the
CPU input will advance the count by one.
One clock should be held HIGH while counting with the other, otherwise the circuit will
either count by twos or not at all, depending on the state of the first flip-flop, which cannot
toggle as long as either clock input is LOW. Applications requiring reversible operation
must make the reversing decision while the activating clock is HIGH to avoid erroneous
counts.
The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH.
When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW
transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock.
Likewise, the TCD output will go LOW when the circuit is in the zero state and the
CPD goes LOW. The terminal count outputs can be used as the clock input signals to the
next higher order circuit in a multistage counter, since they duplicate the clock waveforms.
Multistage counters will not be fully synchronous, since there is a slight delay time
difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load capability of the circuit.
Information present on the parallel data inputs (D0 to D3) is loaded into the counter and
appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when
the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will
disable the parallel load gates, override both clock inputs and set all outputs (Q0 to
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the
next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will
be counted.
2. Features
I
I
I
I
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74HC193D
74HC193DB
74HC193N
74HC193PW
74HCT193D
74HCT193DB
74HCT193N
74HCT193PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SO16
SSOP16
DIP16
TSSOP16
SO16
SSOP16
DIP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic dual in-line package; 16 leads (300 mil)
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic dual in-line package; 16 leads (300 mil)
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT38-4
SOT403-1
SOT109-1
SOT338-1
SOT38-4
SOT403-1
Type number
4. Functional diagram
15
D0
1
D1
10
D2
9
D3
TCU
COUNTER
TCD
12
13
CPU
14
MR
FLIP-FLOPS
Q0
3
2
Q1
6
Q2
7
Q3
001aag405
11
5
4
PL
CPU
CPD
PL
11
5
4
14
MR
D0
15
D1
1
D2
10
D3
9
12
13
TCU
TCD
CPD
3
Q0
2
Q1
6
Q2
7
Q3
001aag409
Fig 1. Functional diagram
74HC_HCT193_3
Fig 2. Logic symbol
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 23 May 2007
2 of 29
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
74HC193
74HCT193
D1
1
2
3
4
5
6
7
8
001aaf408
74HC193
74HCT193
D1
Q1
Q0
CPD
CPU
Q2
Q3
GND
1
2
3
4
5
6
7
8
001aag406
16 V
CC
15 D0
14 MR
13 TCD
12 TCU
11 PL
10 D2
9
D3
D1
Q1
Q0
CPD
CPU
Q2
Q3
GND
1
2
3
4
5
6
7
8
001aag407
16 V
CC
15 D0
14 MR
13 TCD
12 TCU
11 PL
10 D2
9
D3
74HC193
74HCT193
16 V
CC
15 D0
14 MR
13 TCD
12 TCU
11 PL
10 D2
9
D3
Q1
Q0
CPD
CPU
Q2
Q3
GND
Fig 5. Pin configuration SO16
Fig 6. Pin configuration TSSOP16
and SSOP16
Fig 7. Pin configuration DIP16
5.2 Pin description
Table 2.
Symbol
D0
D1
D2
D3
Q0
Q1
Q2
Q3
CPD
CPU
GND
PL
TCU
TCD
MR
V
CC
[1]
Pin description
Pin
15
1
10
9
3
2
6
7
4
5
8
11
12
13
14
16
Description
data input 0
data input 1
data input 2
data input 3
flip-flop output 0
flip-flop output 1
flip-flop output 2
flip-flop output 3
count down clock input
[1]
count up clock input
[1]
ground (0 V)
asynchronous parallel load input (active LOW)
terminal count up (carry) output (active LOW)
terminal count down (borrow) output (active LOW)
asynchronous master reset input (active HIGH)
supply voltage
LOW-to-HIGH, edge triggered.
74HC_HCT193_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 23 May 2007
5 of 29
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