HV57708
32MHz, 64-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
►
►
►
►
►
►
►
►
►
►
HVCMOS
®
technology
5.0V CMS Logic
Output voltage up to +80V
Low power level shifting
32MHz equivalent data rate
Latched data outputs
Foreward and reverse shifting options (DIR pin)
Diode to VPP allows efficient power recovery
Outputs may be hot switched
Hi-Rel processing available
as driving plasma panels, vacuum fluorescent displays, or
large matrix LCD displays.
The device has 4 parallel 16-bit registers, permitting data
rates 4x the speed of one (they are clocked together). There
are also 64 latches and control logic to perform the polarity
select and blanking of the outputs. HV
OUT
1 is connected to
the first stage of the first shift register through the polarity
and blanking logic. Data is shifted through the shift registers
on the logic low to high transition of the clock. The DIR pin
causes CCW shifting when connected to GND, and CW
shifting when connected to VDD. A data output buffer is
provided for cascading devices. This output reflects the
current status of the last bit of the shift register (HV
OUT
64).
Operation of the shift register is not affected by the LE (latch
enable), BL (blanking), or the POL (polarity) inputs. Transfer
of data from the shift registers to the latches occurs when
the LE input is high. The data in the latches is stored when
the LE is low.
General Description
The HV57708 is a low voltage serial to high voltage
parallel converter with push-pull outputs. The device has
been designed for use as a driver for EL displays. It can
also be used in any application requiring multiple output
high voltage current sourcing and sinking capability such
Functional Block Diagram
D O1
D
I
4
D O2
D I3
D O3
D I2
D O4
D I1
V DD
LE
BL
POL
V PP
DIR
SR1
HV
OUT
1
5
9
•
•
•
HV
OUT
61
SR2
HV
OUT
2
6
10
•
•
•
HV
OUT
62
CLK
HV
OUT
3
7
11
•
•
•
HV
OUT
63
SR3
SR4
HV
OUT
4
8
12
•
•
•
HV
OUT
64
Note:
Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc.
D O4
DI1
D O3
DI2
D O2
DI3
D O1
DI4
GND
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV57708
Ordering Information
Package Options
Device
20.00x14.00mm body
3.40mm height (max)
0.80mm pitch
80-Lead PQFP
HV57708
HV57708PG-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
Value
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD
Output voltage , V
PP
Logic input levels
Ground current
1
Continuous total power dissipation
2
Operating temperature range
Storage temperature range
Lead temperature
3
-0.5V to +7.5V
-0.5V to +90V
-0.3V to V
DD
+0.3V
1.5A
1200mW
-40°C to +85°C
-65°C to +150°C
260°C
80
1
80-Lead PQFP (PG)
(top view)
Product Marking
Top Marking
HV57708P G
LLLLLLLLLL
Y YW W
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Notes:
1. Limited by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C.
3. 1.6mm (1/16inch) from case for 10 seconds.
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
80-Lead PQFP (PG)
Recommended Operating Conditions
Sym
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
Parameter
Logic supply voltage
Output voltage
High-level input voltage
Low-level input voltage
Clock frequency per register
Operating free-air temperature
Min
4.5
8.0
V
DD
-0.5V
0
-
-40
Max
5.5
80
-
0.5
8.0
+85
Units
V
V
V
V
MHz
°C
Notes:
Power-up sequence should be the following:
1. Apply ground.
2. Apply V
DD
.
3. Set all inputs (D
IN
, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV57708
DC Electrical Characteristics
(Over recommended operating conditions unless otherwise noted)
Sym
I
DD
I
PP
I
DDQ
V
OH
V
OL
I
IH
I
IL
V
OC
Parameter
V
DD
supply current
High voltage supply current
Quiescent V
DD
supply current
High level output
Low level output
HV
OUT
Data out
HV
OUT
Data out
Min
-
-
-
-
65
V
DD
-0.5
-
-
-
-
-
A
Max
15
100
100
100
-
-
7.0
0.5
1.0
-1.0
1.0
Units
mA
µA
µA
µA
V
V
V
V
µA
µA
V
Conditions
V
DD
= V
DD
max, f
CLK
= 8.0MHz
Outputs high
Outputs low
All V
IN
= V
DD
I
O
= -15mA, V
PP
= +80V
I
O
= -100µA
I
O
= 12mA, V
PP
= +80V
I
O
= 100µA
V
IH
= V
DD
V
IL
= 0V
I
OC
= 1.0mA
High-level logic input current
Low-level logic input current
High voltage clamp diode
AC Electrical Characteristics
(T
Sym
f
CLK
t
WL
, t
WH
t
SU
t
H
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
*
t
WLE
t
SLE
Parameter
Clock frequency
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
Time from latch enable to HV
OUT
= 85°C max. Logic signal inputs and Data inputs have t
r
, t
f
≤ 5ns [10% and 90% points])
Min
-
62
10
15
-
-
-
25
25
0
Max
8.0
-
-
-
500
70
70
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Per register
---
---
---
C
L
= 15pF
C
L
= 15pF
C
L
= 15pF
---
---
---
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
LE pulse width
LE set-up time before clock rises
* t
DLE
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR
output to stabilize).
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV57708
Input and Output Equivalent Circuits
V DD
V DD
V PP
Input
Data Out
HV
OUT
GND
Logic Inputs
GND
Logic Data Output
GND
High Voltage Outputs
Switching Waveforms
V IH
Data Input
50%
t
SU
Clock
50%
t
WL
50%
t
WH
50%
Data Out
t
DLH
50%
t
DHL
50%
t
DLE
t
WLE
50%
t
SLE
90%
10%
t
OFF
HV OUT
w/ S/R HIGH
90%
V OH
V OL
V OH
V OL
V OH
V OL
Data Valid
t
H
90%
50%
50%
V IL
t
f
t
r
V IH
10%
10%
90%
50%
V IL
V OH
V OL
V IH
V OL
Latch Enable
HV OUT
w/ S/R LOW
10%
t
ON
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV57708
Function Table
Inputs
Function
All O/P high
All O/P low
O/P normal
O/P inverted
Data falls
through
(latches
transparent)
Data stored/
latches loaded
Data
X
X
X
X
L
H
L
H
X
X
D
I/O
1-4A
I/O relation
D
I/O
1-4A
D
I/O
1-4B
D
I/O
1-4B
CLK
X
X
X
X
_
_↑
_
_↑
_
_↑
_
_↑
X
X
_
_↑
_
_↑
_
_↑
_
_↑
LE
X
X
X
X
H
H
H
H
L
L
H
L
L
H
BL
L
L
H
H
H
H
H
H
H
H
H
H
H
H
POL
L
H
H
L
H
H
L
L
H
L
H
H
H
H
DIR
X
X
X
X
X
X
X
X
X
X
H
H
L
L
Shift Reg
-
-
-
-
L
H
L
H
*
*
Q
n
→Q
n+1
Q
n
→Q
n+1
Q
n
→Q
n-1
Q
n
→Q
n-1
Outputs
HV Outputs
H
L
No inversion
Inversion
L
H
H
L
Stored Data
Inversion of
stored data
New H or L
Previous H or L
Previous H or L
New H or L
Data Out
-
-
-
-
-
-
-
-
-
-
D
I/O
1-4B
D
I/O
1-4B
D
I/O
1-4A
D
I/O
1-4A
Note:
* = dependent on previous stage’s state. See Pin configuration for DIN and DOUT pin designation for CW and CCW shift.
Shift Register Operation
HV
OUT
32
•
•
•
DIR = H; CW (HV
DIR = L; CCW (HV
OUT
1
→
HV
OUT
64)
OUT
64
→
HV
OUT
1)
H
OUT
33
•
•
•
DIR = H
1
SR1
SR2
SR3
SR4
DIR = L
4
3
•
2
•
3
•
4
HV
OUT
2
HV
OUT
1
Pin
25 26 27 28
2
•
1
H
OUT
63
H
OUT
64
36 37 38 39
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
汽车电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
