HV507
64-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
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Processed with HVCMOS
®
technology
Operating output voltages to 300V
Low power level shifting from 5.0 to 300V
Shift register speed: 8.0MHz @ V
DD
= 5.0V
64 latched data outputs
Output polarity and blanking
CMOS compatible inputs
Foreward and reverse shifting options
General Description
The HV507 is a low voltage serial to high voltage parallel
converter with 64 push-pull outputs. This device has been
designed for use as a printer driver for electrostatic applications.
It can also be used in any application requiring multiple output,
high voltage, low current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through
the device. With DIR grounded, D
IO
A is Data-In and D
IO
B is
Data-Out; data is shifted from HV
OUT
64 to HV
OUT
1. When DIR
is at logic high, D
IO
B is Data-In and D
IO
A is Data-Out: data is
then shifted from HV
OUT
1 to HV
OUT
64. Data is shifted through
the shift register on the low to high transition of the clock. Data
output buffers are provided for cascading devices. Operation
of the shift register is not affected by the LE (latch enable), BL
(blanking), or the POL(polarity) inputs. Transfer of data from the
shift register to the latch occurs when the LE is high. The data in
the latch is stored during LE transition from high to low.
Functional Block Diagram
POL
BL
Latch Enable
D
IO
A
VPP
L/T
HV
OUT
1
Clock
L/T
HV
OUT
2
•
•
•
60 Additional
Outputs
•
•
•
HV
OUT
63
DIR
64 bit
Static Shift
Register
64 Latches
L/T
L/T
HV
OUT
64
D
IO
B
L/T = Level Translator
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV507
Ordering Information
Package Option
Device
80-Lead Quad Plastic Gullwing
20.00x14.00mm body
3.40mm height (max)
0.65mm pitch
HV507
HV507PG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD
Supply voltage, V
PP
Logic input levels
Ground current
2
High voltage supply current
1
Pin Configuration
Value
-0.5V to +6.0V
V
DD
to +320V
-0.5V to V
DD
+0.5V
0.5A
0.5A
1200mW
0°C to +70°C
-65°C to +150°C
80
1
Continuous total power dissipation
2
Operating temperature range
Storage temperature range
80-Lead Quad Plastic Gullwing (PG)
(top view)
Product Marking
HV507PG
LLLLLLLLLL
YYWW
CCCCCCCC AAA
L = Lot Number
YY = Year Sealed
WW = Week Sealed
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to GND.
Notes:
1. Connection to all power and ground pads is required. Duty cycle is
limited by the total power dissipated in the package.
2. For operation above 25°C ambiant derate linearly to 70
O
C at 26.7mW/
°C.
80-Lead Quad Plastic Gullwing (PG)
Recommended Operating Conditions
Sym
V
DD
V
PP
V
IH
V
IL
T
A
Parameter
Logic supply voltage
High voltage supply
High-level input voltage
Low-level input voltage
Operating free-air temperature
Min
4.5
60
V
DD
-0.9
0
0
Typ
5.0
-
-
-
-
Max
5.5
300
V
DD
0.9
+70
Units
V
V
V
V
°C
Power-up sequence should be the following:
1. Connect ground
2. Apply V
DD
3. Set all inputs (Data, CLK, Enable, etc.) to a known state
4. Apply V
PP
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV507
Electrical Characteristics
DC Characteristics
(For V
Sym
I
DD
I
DDQ
I
PP
I
IH
I
IL
V
OH
V
OL
V
OC
Parameter
V
DD
supply current
Quiescent V
DD
supply current
High voltage supply current
High-level logic input current
Low-level logic input current
High level output
Low level output
HV
OUT
clamp voltage
DD
DD
= 5.0V, V
PP
= 300V, T
A
= 25°C)
Min
-
-
-
-
-
-
265
V
DD
-1.0V
-
-
-
-
= 5.0V, V
PP
= 300V, T
A
= 25°C)
Max
15
200
0.50
0.50
10
-10
-
-
35
1.0
V
PP
+1.5V
-30
Units
mA
µA
mA
µA
µA
V
V
V
Conditions
f
CLK
= 8.0MHz, F
DATA
= 4.0MHz, LE = low
All V
IN
= 0 or V
DD
V
PP
= 300V. All outputs high.
V
PP
= 300V. All outputs low.
V
IH
= V
DD
V
IL
= 0V
V
PP
= 300V, IHV
OUT
= -1.0mA,
ID
OUT
= -100µA
V
DD
= 5.0V, IHV
OUT
= +1.0mA,
ID
OUT
= +100µA
I
OC
= +1.0mA
I
OC
= -1.0mA
HV
OUT
Data Out
HV
OUT
Data Out
AC Characteristics
1
(For V
Sym
f
CLK
t
W
t
SU
t
H
t
WLE
t
DLE
t
SLE
t
ON,
t
OFF
t
DHL
t
DLH
t
R
, t
F
Parameter
Clock frequency
Min
-
62
35
30
80
35
40
-
-
-
-
Max
8.0
-
-
-
-
-
-
4.0
125
125
5.0
Units
MHz
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
Conditions
---
---
---
---
---
---
---
C
L
= 20pF
C
L
= 20pF
C
L
= 20pF
---
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
LE pulse width
Delay time clock to LE high to low
LE set-up time before clock rises
Time from LE to HV
OUT
Delay time clock to data high to low
Delay time clock to data low to high
All logic inputs
Note:
1. Shift register speed can be as low as DC as long as data set-up and hold time meet the spec.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV507
Input and Output Equivalent Circuits
VDD
VDD
VPP
Input
Data Out
HV
OUT
GND
Logic Inputs
GND
Logic Data Output
HVGND
High Voltage Outputs
Switching Waveforms
V
IH
Data In
(D
IO
A/D
IO
B)
50%
t
SU
CLK
50%
t
WL
50%
t
WH
50%
Data Out
(D
IO
A/D
IO
B)
t
DLH
50%
t
DHL
50%
t
DLE
t
WLE
50%
t
SLE
90%
10%
t
OFF
HV
OUT
w/ S/R HIGH
90%
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
IH
V
OL
Data Valid
t
H
V
IH
50%
50%
V
IL
V
OH
V
OL
50%
V
IL
Latch Enable
HV
OUT
w/ S/R LOW
10%
t
ON
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV507
Function Table
Inputs
Function
Data
X
X
X
H or L
X
X
L
H
D
IO
A
D
IO
B
CLK
X
X
X
↑
X
X
↑
↑
↑
↑
LE
X
X
L
L
↓
↓
H
H
X
X
BL
L
L
H
H
H
H
H
H
X
X
POL
L
H
L
H
H
L
H
H
X
X
DIR
X
X
X
X
X
X
X
X
L
H
Shift Reg
1
*
*
*
H or L
*
*
L
H
Q
N
→
Q
N
→
2...64
*...*
*...*
*...*
*...*
*...*
*...*
*...*
*...*
Q
N+1
Q
N+1
Outputs
HV Outputs
1
H
L
*
*
*
*
L
H
-
-
2...64
H...H
L...L
*...*
*...*
*...*
*...*
*...*
*...*
Data Out
*
*
*
*
*
*
*
*
*
D
IO
B
D
IO
A
All on
All off
Invert mode
Load S/R
Store data in
latches
Transparent
latch mode
I/O Relation
Notes:
H = high level, L = low level = 0V, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition.
* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
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