HV301
Hot Swap Controller
Features
►
10 to 90V operation, positive or negative
supply
►
UV/OV lock out & power-on-reset
►
Circuit breaker
►
100ms startup timer
►
Automatic retry or latched operation
►
Low Power, 400µA sleep mode
►
8-Lead SOIC Package
General Description
The Supertex HV301 Hot Swap Controller provides inrush current limiting and
other power supply support functions for hot swap equipment. Current limiting is
provided by control of an external MOSFET which is placed in the return line of
the power supply connection. Placement in the return allows use of an N-channel
MOSFET without the need for high side driving.
An internal clamp at the GATE pin activates when full bias for the HV301 is not
available, thus keeping the MOSFET in the off-state during the initial insertion
phase. As soon as adequate bias is available for the main control circuits, the UV
(undervoltage) and OV (overvoltage) pins check for normal operating voltage on
the power supply input.
Once normal operating voltage is present, the GATE voltage for the external
MOSFET ramps up at a constant rate. The rate is controlled by the value of an
external capacitor placed at the RAMP pin. At some point the external MOSFET
channel is enhanced, allowing power supply current to flow, thereby energizing
downstream power supply capacitors.
During the GATE ramp up the power supply current is monitored with the aid
of an external sense resistor which forces reduction in the ramp rate when the
power supply current reaches a set limit. The limit is set by the value of the
external sense resistor and the threshold of the current sense amplifier (50mV).
Once inrush current subsides or the drain voltage ceases to drop, the GATE
voltage resumes its rise to the output voltage of an internal regulator V
REG
, with
an output voltage ranging from 8.5 to 12V. When GATE is within 1.2V of V
REG
,
GATE is pulled high to V
REG
with an internal switch, the open-drain PWRGD pin
is released to high impedance, and the HV301 enters a low power mode.
The HV301 includes a start-up timer and a circuit breaker function to protect the
MOSFET from excessive power dissipation. The start-up timer trips when the
start-up phase exceeds 100ms. The circuit breaker trips at double the current
limit threshold (100mV). Upon tripping of either the start-up timer or the circuit
breaker the MOSFET is turned off, and the PWRGD pin is pulled low. Thereafter,
a programmable automatic retry timer allows the MOSFET to cool down before
resetting and restarting. The automatic retry can be disabled by adding an
external resistor at the RAMP pin (about 2.5MΩ, see applications section).
Applications
►
►
►
►
►
►
►
►
►
48V central office switching
24V cellular and fixed wireless systems
24V PBX systems
Line cards
48V powered ethernet for VoIP
Distributed power systems
Power supply control
48V storage networks
Electronic circuit breaker
Typical Application Circuit
GND
R1
487kΩ
R2
6.81kΩ
8
VDD
3
UV
PWRGD
1
ENABLE
HV301
SENSE
GATE
+5.0V
C
LOAD
2
OV
VEE
RAMP
C1
10nF
7
DC/DC
PWM
CONVERTER
COM
R3
9.76kΩ
-48V
4
5
6
-48V
R4
12.5mΩ
Q1
IRF530
NOTES:
1. Undervoltage threshold (UV) set to 35V.
2. Overvoltage threshold (OV) set to 65V.
3. Startup current set to 4A.
4. Circuit breaker set to 8A.
5. 100ms max startup time.
6. Automatic retry enabled.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV301
Ordering Information
Package Options
Device
8-Lead SOIC (Narrow Body)
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
HV301
HV301LG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
DD
(referenced to V
EE
)
V
PWRGD
(referenced to V
EE
)
V
UV
and V
OV
(referenced to V
EE
)
Operating ambient temperature, T
J
Operating junction temperature, T
J
Storage temperature range, T
S
Value
-0.3V to +100V
-0.3V to +100V
-0.3V to +12V
-40°C to +85°C
-40°C to +125°C
-65°C to +150°C
Pin Configuration
PWRGD
1
OV
2
UV
3
VEE
4
8
7
6
5
VDD
RAMP
GATE
SENSE
8-Lead SOIC (LG)
Product Marking
HV301
YWW
LLLL
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
8-Lead SOIC (LG)
Electrical Characteristics
(-40 C to +85°C unless otherwise specified, all voltages are referenced to V
O
EE
)
Sym
Supply
V
DD
I
DD
Parameter
Supply voltage
Supply current
Standby mode supply current
Rising threshold
Falling threshold
Hysteresis
Input current
1
Current limit threshold voltage
Circuit breaker threshold voltage
Min
10
-
-
-
-
-
-
40
80
Typ
-
600
400
1.26
1.16
100
-
50
100
Max
90
700
450
-
-
-
1.0
60
120
Units
V
µA
µA
V
V
mV
nA
mV
mV
Conditions
---
V
DD
= 48V, mode = limiting
V
DD
= 48V, mode = standby
Low to high transition
High to low transition
---
V
UV
= 1.9V
V
UV
= 1.9V, V
OV
= 0.5V
V
UV
= 1.9V, V
OV
= 0.5V
OV and UV Comparators
V
RTH
V
FTH
V
HYS
I
V
CL
V
CB
Current Limit
Notes:
1. Guaranteed by design.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV301
Electrical Characteristics
(-40 C to +85°C unless otherwise specified, all voltages are referenced to V
O
EE
)
Sym
V
GATE
I
GATEUP
I
GATEDOWN
I
RAMP
t
POR
t
RISE
t
LIMIT
t
PWRGD
V
RAMP
t
STARTLIMIT
t
CBTRIP
t
AUTO
V
PWRGD(HI)
V
PWRGD(LO)
t
GATEHLOV
t
GATEHLUV
Parameter
Maximum GATE drive voltage
GATE drive pull-up current
GATE drive pull-down current
Ramp pin output current
Time from UV to GATE turn on
1
Time from GATE turn on to V
SENSE
limit
Duration of current limit mode
Time from current limit to PWRGD
Voltage on ramp pin in current limit mode
2
Start up time limit
Circuit breaker delay time
Automatic restart delay time
Power good pin breakdown voltage
Power good pin output low voltage
OV delay
UV delay
Min
8.5
500
40
-
2.0
400
-
-
-
80
2.0
12
90
-
-
-
Typ
10
-
-
10
-
-
5.0
5.0
3.6
100
-
-
-
0.5
-
-
Max
12
-
-
-
-
-
-
-
-
120
5.0
-
-
0.8
500
500
Units
V
µA
mA
µA
ms
µs
ms
ms
V
ms
µs
s
V
V
ns
ns
Conditions
V
UV
= 1.9V, V
OV
= 0.5V
V
UV
= 1.9V, V
OV
= 0.5V
V
UV
= 0V, V
OV
= 0.5V
V
SENSE
= 0V
---
---
---
---
---
---
May be extended by external RC
circuit
---
PWRGD is high
I
PWRGD
= 1.0mA, PWRGD is low
---
---
Gate Drive Output
Ramp Timing Control
(Test conditions: C
LOAD
= 100µF, C
RAMP
= 10nF, V
UV
= 1.9V, V
OV
= 0.5V, External MOSFET is IRF530
3
)
Power Good Output
Dynamic Characteristics
Notes:
1. This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
2. This voltage depends on the characteristics of the external N-Channel MOSFET. V
th
= 3.0V for an IRF530.
3. IRF530 is a registered trademark of International Rectifier.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV301
Functional Block Diagram
UV
C
Regulator & POR
VDD
V
BG
OV
~9.8V
C
UVLO
Logic
P
U
L
L
H
I
G
H
PWRGD
C
D
I
S
A
B
L
E
V
REG
10µA
2V
BG
1 : 2
mirror
GATE
RAMP
SENSE
Transconductor
Transconductor
5kΩ
gm
5k
V
EE
Clamp Mechanism
Functional Description
The HV301 provides control over the power supply cur-
rent on systems where circuit cards are inserted into live
backplanes. Such systems can frequently be found in the
telecom, data networking and computing industry. The de-
vice provides means of limiting the power supply current af-
ter contact with the live backplane is made, thereby protect-
ing card and backplane connectors and reducing the voltage
disturbance on the backplane’s power supply. Additional
protection is provided in the form of a circuit breaker function
and a start-up time limiter, both for protection of the external
MOSFET and the system as a whole.
Start-up Sequence
After first contact is made with the backplane, the HV301
tries to establish an internal bias supply of 10V. During this
time, GATE, PWRGD and RAMP are positively held low by
circuitry that can operate with partial supply voltage.
When the internal bias supply is in regulation, the undervoltage
(UV) and overvoltage (OV) comparators start monitoring the
external power supply. External resistor dividers at UV and
OV pin set the window for normal operating supply voltage.
These may be two individual dividers, or a single divider with
two taps, as shown in the application diagrams.
Once the power supply voltage is within normal operating
range, a 10μA internal source turns on to charge an external
capacitor at the RAMP pin. The voltage at the GATE output
follows the RAMP pin voltage with an offset of about 2.5V for
control of the external MOSFET.
Power supply current starts to flow once the GATE voltage
reaches the MOSFET threshold voltage, which is typically
in the 2.0 to 4.0V range. The current sense amplifier at the
SENSE pin reduces the RAMP charging current in propor-
tion to the supply current, thereby slowing the voltage rise
at RAMP, and thus the rise of the GATE voltage. At a sense
voltage of 50mV the RAMP current is reduced to zero, and
the RAMP and GATE voltages stop rising, thereby prevent-
ing a further rise in the power supply current.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV301
Functional Description
(cont.)
Once external power supply capacitors are charged, the
power supply current subsides, and the RAMP current in-
creases again to its maximum value of 10μA. The RAMP
and GATE voltages resume their rise. When the RAMP volt-
age is within 1.2V of the internal supply, then GATE is con-
nected to the internal supply, and the open-drain PWRGD
pin is released, marking the end of the start-up.
If the start-up sequence is not finished within 100ms, then
the internal start-up timer causes a reset of the RAMP and
GATE voltage to 0V, and the automatic retry timer is started
to allow the MOSFET to cool off. After the retry delay a new
startup sequence is initiated if the power supply voltage is
within the normal operating range, as determined by the UV
and OV comparators.
The circuit breaker monitors the sense amplifier for the pres-
ence of an overcurrent condition at all times. The overcur-
rent threshold is set at twice the maximum inrush current
threshold. Should overcurrent occur, then RAMP, GATE, and
PWRGD are brought to zero, and the automatic retry timer
is started.
The automatic retry timer can be disabled by attachment of
an additional resistor at the RAMP pin if a latched shutdown
is desired.
A further reduction in the ramp rate of the RAMP and GATE
voltages can be attained by connection of a feedback ca-
pacitor from the drain node to the RAMP pin. During startup
the drain voltage drops at a rate proportional to the inrush
current. This falling voltage waveform can be used to fur-
ther reduce the current that flows onto the RAMP capacitor,
thereby reducing the maximum inrush current.
Design Information
Setting up the UV and OV comparators
The following example shows how the resistors for the
threshold setting divider can be determined. The procedure
applies to the (R1, R2, R3) divider having two taps as shown
on the typical applications diagram.
The following procedure bases the selection of the divider
resistors on specification of the shutdown / disable voltages.
A similar procedure can be devised that bases selection on
specification of the enable voltages.
Let’s assume the following:
• nominal divider current draw I
NOM
= 100μA,
• nominal power supply voltage V
NOM
= 50V,
• overvoltage shutdown voltage V
OVS
= 65V,
• undervoltage shutdown voltage V
UVS
= 35V,
• negligible (UV, OV) comparator input currents,
• Comparator rising threshold V
RTH
= 1.26V
• Comparator falling threshold V
FTH
= 1.16V
The following applies:
• R
123
= (R
1
+ R
2
+ R
3
)
• R
123
= V
NOM
/ I
NOM
• R
123
= 500kΩ
R
3
follows from the OV shutdown voltage:
• DF
OV
= R
3
/ R
123
• V
RTH
= V
OVS
· DF
OV
• R
3
= R
123
· V
RTH
/ V
OVS
• R
3
= 9.692kΩ (97.6k 1%)
R
2
follows from the UV shutdown voltage:
• DF
UV
= (R
2
+ R
3
) / R
123
• V
FTH
= V
UVS
· DF
UV
• R
2
+ R
3
= R
123
· V
FTH
/ V
UVS
• R2 = 6.879kΩ (6.81k 1%)
And:
• R1 = 483.429kΩ (487k 1%)
Now the upper and lower enable voltages can be deter-
mined:
• Lower Enable Voltage V
LEN
• Upper Enable Voltage V
UEN
• V
RTH
= DF
UV
· V
LEN
• V
FTH
= DF
OV
· V
UEN
• V
LEN
= 38.0V
• V
UEN
= 59.8V
Programming Maximum Inrush Current and Circuit
Breaker Current
The values of the current limit threshold voltage V
CL
and the
external current sense resistor R
CS
determine the maximum
power supply current during startup I
MAX
(the maximum in-
rush current). Similarly the circuit breaker trip current I
CB
is
determined by the values of the circuit breaker threshold
voltage V
CB
and the value of R
CS
.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
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