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LAN91C100FDTQFP概述

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LAN91C100FD REV. D

FEAST Fast Ethernet

Controller with Full

Duplex Capability

Datasheet

Product Features

Dual Speed CSMA/CD Engine (10 Mbps and 100

Mbps)

Compliant with IEEE 802.3 100BASE-T

Specification

Supports 100BASE-TX, 100BASE-T4, and

10BASE-T Physical Interfaces

32 Bit Wide Data Path (into Packet Buffer

Memory)

Support for 32 and 16 Bit Buses

Support for 32, 16 and 8 Bit CPU Accesses

Synchronous, Asynchronous and Burst DMA

Interface Mode Options

128 Kbyte External Memory

Built-In Transparent Arbitration for Slave

Sequential Access Architecture

Flat MMU Architecture with Symmetric

Transmit and Receive Structures and

Queues

MII (Media Independent Interface) Compliant

MAC-PHY Interface Running at Nibble Rate

MII Management Serial Interface

Seven Wire Interface to 10 Mbps ENDEC

EEPROM-Based Setup

Full Duplex Capability

ORDER NUMBER(S):

LAN91C100-FD for 208-pin QFP package

LAN91C100-FD-SS for 208-pin QFP lead-free RoHS compliant package

LAN91C100-FD for 208-pin TQFP package

LAN91C100-FD-ST for 208-pin TQFP lead-free RoHS compliant package

SMSC LAN91C100FD Rev. D

Page 1

Revision 1.0 (09-22-08)

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY

DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR

REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC

OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO

HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

Revision 1.0 (09-22-08)

Page 2

SMSC LAN91C100FD Rev. D

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability

Table Of Contents

Chapter 1

Chapter 2

Chapter 3

Chapter 4

4.1

4.2

4.1.1

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.2.7

General Description ............................................................................................................. 5

Pin Configuration................................................................................................................. 6

Description of Pin Functions ............................................................................................... 7

Functional Description....................................................................................................... 15

Clock Generator Block............................................................................................................................15

DMA Block..............................................................................................................................................15

Arbiter Block ...........................................................................................................................................15

MMU Block .............................................................................................................................................16

BIU Block................................................................................................................................................16

MAC-PHY Interface Block ......................................................................................................................16

MII Management Interface Block ............................................................................................................17

Serial EEPROM Interface .......................................................................................................................17

Description of Block........................................................................................................................... 15

CSMA/CD BLOCK............................................................................................................................. 15

Chapter 5

5.1

5.2

5.3

5.4

5.5

5.6

Data Structures and Registers .......................................................................................... 19

Packet Format in Buffer Memory ...................................................................................................... 19

Typical Flow of Events for Transmit (Auto Release = 0)................................................................... 41

Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 42

Typical Flow of Events for Receive ................................................................................................... 43

Memory Partitioning .......................................................................................................................... 48

Interrupt Generation .......................................................................................................................... 49

Chapter 6

Chapter 7

7.1

7.2

7.3

7.4

8.1

8.2

Board Setup Information .................................................................................................. 52

Application Considerations ............................................................................................... 55

Fast Ethernet Slave Adapter ............................................................................................................. 55

VL Local Bus 32 Bit Systems ............................................................................................................ 55

High End ISA or Non-Burst EISA Machines...................................................................................... 58

EISA 32 Bit SLAVEEISA 32 Bit Slave............................................................................................... 60

Chapter 8

Operational Description .................................................................................................... 63

Maximum Guaranteed Ratings* ........................................................................................................ 63

DC Electrical Characteristics............................................................................................................. 63

Chapter 9

Chapter 10

Timing Diagrams................................................................................................................ 66

Package Outlines............................................................................................................. 76

List of Figures

Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13

Figure 3.2 - LAN91C100FD System Diagram ..............................................................................................................14

Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18

Figure 5.1 - Data Packet Format ..................................................................................................................................19

Figure 5.2 - Interrupt Structure .....................................................................................................................................37

Figure 5.3 - Interrupt Service Routine ..........................................................................................................................44

Figure 5.4 - RX INTR ...................................................................................................................................................45

Figure 5.5 - TX INTR....................................................................................................................................................46

Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) ......................................................................47

Figure 5.7 - Drive Send and Allocate Routines ............................................................................................................48

Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................51

Figure 6.1 - 64 X 16 Serial EEPROM Map...................................................................................................................54

SMSC LAN91C100FD Rev. D

Page 3

Revision 1.0 (09-22-08)

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability

Figure 7.1 - LAN91C100FD on VL BUS.......................................................................................................................57

Figure 7.2 - LAN91C100FD on ISA Bus.......................................................................................................................59

Figure 7.3 - LAN91C100FD on EISA Bus ....................................................................................................................62

Figure 9.1 - Asynchronous Cycle - nADS=0.................................................................................................................66

Figure 9.2 - Asynchronous Cycle - Using nADS...........................................................................................................67

Figure 9.3 - Asynchronous Cycle - nADS=0.................................................................................................................68

Figure 9.4 - Burst Write Cycles - nVLBUS=1 ...............................................................................................................69

Figure 9.5 - Burst Read Cycles - nVLBUS=1 ...............................................................................................................70

Figure 9.6 - Address Latching for all Modes.................................................................................................................71

Figure 9.7 - Synchronous Write Cycles - nVLBUS=0...................................................................................................71

Figure 9.8 - Synchronous Read Cycle - NVLBUS=0....................................................................................................72

Figure 9.9 - SRAM Interface ........................................................................................................................................73

Figure 9.10 - ENDEC Interface - 10 Mbps ...................................................................................................................74

Figure 9.11 - MII Interface............................................................................................................................................75

Figure 10.1 - 208 Pin QFP Package Outline ................................................................................................................76

Figure 10.2 - 208 Pin TQFP Package Outlines ............................................................................................................77

List of Tables

Table 3.1 - LAN91C100FD Pin Requirements

Table 5.1 - Internal I/O Space Mapping

Table 7.1 - VL Local Bus Signal Connections

Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors

Table 7.3 - EISA 32 Bit Slave Signal Connections

Table 10.1 - 208 Pin QFP Package Parameters

Table 10.2 - 208 Pin TQFP Package Outlines

Revision 1.0 (09-22-08)

Page 4

SMSC LAN91C100FD Rev. D

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability

Chapter 1

General Description

The LAN91C100FD is designed to facilitate the implementation of first generation Fast Ethernet adapters

and connectivity products. For this first generation of products, flexibility dominates over integration. The

LAN91C100FD is a digital device that implements the MAC portion of the CSMA/CD protocol at 10 and

100 Mbps, and couples it with a lean and fast data and control path system architecture to ensure the CPU

to packet RAM data movement does not cause a bottleneck at 100 Mbps.

Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding

packets. The LAN91C100FD is software compatible with the LAN9000 family of products and can use existing

LAN9000 drivers (ODI, IPX, and NDIS) in 16 and 32 bit Intel X86 based environments.

Memory management is handled using a unique MMU (Memory Management Unit) architecture and a 32-

bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and

reception for superior data throughput and optimal performance. It also dynamically allocates buffer

memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from

performing these housekeeping functions. The total memory size is 128 Kbytes (external), equivalent to a

total chip storage (transmit and receive) of 64 outstanding packets.

FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The Bus

Interface Unit (BIU) can handle synchronous as well as asynchronous buses, with different signals being

used for each one. FEAST's bus interface supports synchronous buses like the VESA local bus, as well

as burst mode DMA for EISA environments. Asynchronous bus support for ISA is supported even though

ISA cannot sustain 100 Mbps traffic. Fast Ethernet could be adopted for ISA-based nodes on the basis of

the aggregate traffic benefits.

Two different interfaces are supported on the network side. The first is a conventional seven wire ENDEC

interface that connects to the LAN83C694 for 10BASE-T and coax 10 Mbps Ethernet networks. The second

interface follows the MII (Media Independent Interface) specification draft standard, consisting of 4 bit wide

data transfers at the nibble rate. This interface is applicable to 10 Mbps or 100 Mbps networks. Three of the

LAN91C100FD’s pins are used to interface to the two-line MII serial management protocol. Four I/O ports

(one input and three output pins) are provided for LAN83C694 configuration.

The LAN91C100FD is based on the LAN91C100 FEAST, functional revision G modified to add full duplex

capability. Also added is a software-controlled option to allow collisions to discard receive packets.

Previously, the LAN91C100 supported a “Diagnostic Full Duplex” mode. Under this mode the transmit

packet is looped internally and received by the MAC. This mode was enabled using the FDUPLX bit in the

TCR. In order to avoid confusion, the new, broader full duplex function of the LAN91C100FD is

designated as Switched Full Duplex, and the TCR bit enabling it is designated as SWFDUP. When the

LAN91C100FD is configured for SWFDUP, it’s transmit and receive paths will operate independently and

some CSMA/CD functions will be disabled. When the controller is not configured for SWFDUP it will follow

the CSMA/CD protocol.

SMSC LAN91C100FD Rev. D

Page 5

Revision 1.0 (09-22-08)

DATASHEET

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描述	以太网 IC non-pci 10/100 ethernet mac

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LAN91C100FDTQFP概述

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