Actel Corporation, Mountain View, CA 94043
© 2009 Actel Corporation. All rights reserved.
Printed in the United States of America
Part Number: 50200077-6
Release: February 2009
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Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Supported Device Families . . . . .
Core Versions . . . . . . . . . . . .
Supported Interfaces . . . . . . . .
Device Utilization and Performance
Memory Requirements . . . . . . .
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.7
.7
.7
.7
10
1
2
Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Licensing . . . . . . . . . . . .
Importing into Libero IDE . . .
Simulation Flows . . . . . . . .
Synthesis in Libero IDE . . . .
Place-and-Route in Libero IDE
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15
17
18
18
18
3
Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Parameters on Core10100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Parameters on Core10100_AHBAPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AHB/APB Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Frame Data and Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Internal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5
Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Core10100—CSR Interface . . . . . .
Core10100—Data Interface . . . . . .
Core10100_AHBAPB—APB Interface
Core10100_AHBAPB—AHB Interface
Core10100-RMII Interface . . . . . . .
Clock and Reset Control . . . . . . . .
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65
65
67
68
68
68
6
Testbench Operation and Modification . . . . . . . . . . . . . . . . . . . . . . 71
User Testbench (Core10100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AHBAPB User Testbench (Core10100_AHBAPB) . . . . . . . . . . . . . . . . . . . . . . . . 72
7
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Usage with Cortex™-M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
A User Testbench Support Routines . . . . . . . . . . . . . . . . . . . . . . . . . 75
v4.0
3
Table of Contents
Core10100 v4.0
VHDL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Verilog Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
B Transmit and Receive Functional Timing Examples . . . . . . . . . . . . . . . 87
Transmit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Receive Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
C List of Document Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
D Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Customer Service . . . . . . . . . . . . . . . . . .
Actel Customer Technical Support Center . . . . .
Actel Technical Support . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center
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101
101
101
101
101
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4
v4.0
Introduction
Core10100 is a high-speed media access control (MAC) Ethernet controller (Figure
1).
It implements Carrier Sense
Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for MAC over an Ethernet
connection. Communication with an external host is implemented via a set of Control and Status registers and the
DMA controller for external shared RAM. For data transfers, Core10100 operates as a DMA master. It automatically
fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention.
Linked list management enables the use of various memory allocation schemes. Internal RAMs are used as configurable
FIFO memory blocks, and there are separate memory blocks for transmit and receive processes. The core has a generic
host-side interface that connects with external CPUs. This host interface can be configured to work with 8-, 16-, or
32-bit data bus widths with big- or little-endian byte ordering.
Transmit Data
RAM
Data
Interface
Transmit
Control
Data
Controller
Transmit
RMII/MII
Receive
RMII/MII
Receive
Control
Control
Interface
Control and Status
Registers and
Control Logic
Receive Data
RAM
Address
RAM
Figure 1 · Core10100 Block Diagram
Figure 2
shows a typical application using Core10100. Typical applications include LAN controllers, AFDX controllers,
and embedded systems.
Figure 1-1 on page 11
shows the primary blocks of Core10100.
Shared
RAM
CPU
(8-, 16-, or 32-bit)
Data Interface Bus
Core10100
Control Interface Bus
RMII/MII
Interface
PHY
Figure 2 · Typical Core10100 Application
v4.0
5
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