HV9906
HV9906 FlexSwitch
Features
Drive one or hundreds of LEDs including White LEDs
Programmable Current Source (mA to A)
Programmable Voltage Source (Steps Up or Down)
Integrator Lock Loop Technology (IL
2
)
o
Built in Soft Start
o
Allows Discontinuous Feedback
o
Eliminates Compensation Components
o
Eliminates Output Averaging Filters
o
Inherent Dither to Reduce EMI
Eliminates High Voltage Input Electrolytic Capacitor
Smallest and Most Reliable Off-Line Solution
Isolated or Non-Isolated Applications
Can be Operated Directly from Rectified AC Mains
10V to 400V Input Range Internal Regulator
<1.5mA Operating Supply Current
Programmable Feed Forward Regulation
Programmable Feedback Sense Threshold (mV to V)
Integrating Differential Sense Feedback
TM
(Simple Off-Line/PFC & >9V DC/DC Switcher)
General Description
The Supertex HV9906 allows the development of the smallest
possible, most reliable, offline and wide DC/DC conversion range
converters for driving LEDs and other applications. The HV9906
combines internally all the components required to operate directly
from the rectified AC line with a feedback mechanism that
eliminates compensation components.
The HV9906 is capable of driving cascaded converters (multi-
converters), which have been shown to provide the best
performance to component count trade off for wide conversion
range applications like off-line converters with or without power
factor correction (PFC). Bulky and unreliable electrolytic capacitors
can be replaced with lower value non-electrolytic ones or
eliminated completely when using HV9906.
Proper choice of external components will allow the programming
of currents from <1mA to several amps.
The HV9906 utilizes a programmable inversely proportional fast
feed forward algorithm to calculate output on time and a novel
Integrating Lock Loop (IL
2
) feedback with programmable threshold
differential sensing. The sensed feedback may be positive or
negative with respect to ground and the signal may be
discontinuous. This algorithm when used with certain multi-
converters such as the flyback-buck, with a fixed load, results in
near constant frequency with only a small dither which helps meet
FCC requirements.
Applications
LED driver
Power Factor Correction
Constant Current or Voltage Source
Battery Charger / PWM Housekeeping Supplies
Traffic Lights / Street Lights
Back Lighting of Flat Panel Displays
Advertising Signs
Typical Application Circuit
1
9/20/2004
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com
HV9906
Absolute Maximum Ratings*
-0.3V to +450V
+V
IN
Input Voltage
-0.3V to +15V
V
DD
V
ON
Pulse Width Control Voltage
-0.3 to +10V
PS & NS Pin Feedback Voltage
-0.3V to +10V
Operating Ambient Temperature Range
-40°C to +85°C
Operating Junction Temperature Range
-40°C to +150°C
Storage Temperature Range
-65°C to +150°C
Thermal Resistance Junction to Ambient, SOIC
159°C/W
Thermal Resistance Junction to Case, SOIC
45°C/W
Thermal Resistance Junction to Ambient, Plastic DIP
110°C/W
Thermal Resistance Junction to Case, Plastic DIP
35°C/W
*All voltages referenced to AGND and PGND connected together.
Ordering Information
Package Options
8 Pin Plastic DIP
8 Pin SOIC
HV9906P
HV9906LG
Electrical Characteristics
(Unless otherwise noted T
A
= 25
°
C)
Symbol
Parameter
Min
Typ
Max
Units
T
A
Conditions
Input Regulator/Vdd Supply
+V
IN
+I
IN
V
DD(REG)
V
DD(REG)
V
UVLO
V
HYST
Input Voltage
Input Current
Internal Regulator Output Voltage
Internal Regulator Output Voltage
Under Voltage Lockout Threshold
Under Voltage Lockout Hysteresis
10
10
8.0
0.50
12
400
1.5
11.5
12.5
V
mA
V
V
V
V
* Typical under UVLO
* Gate pin open and operating at F
MAX
*
*
V
IN
= 12V
V
IN
= 400V
Decaying V
DD
MOSFET Gate Drive Output
t
R
t
F
Rise Time
Fall Time
75
75
nSec
nSec
C
GATE
= 750pF
C
GATE
= 750pF
PWM
P(V
ON
)
P(V
ON
)
P
MAX
f
MIN
f
MAX
Output Pulse Width at V
ON
Output Pulse Width at V
ON
Maximum Output Pulse Width
Minimum Output Frequency
Maximum Output Frequency
10
250
2
215
3.35
17.8
13.5
17
450
300
nSec
uSec
uSec
KHz
KHz
V
ON
= 5.0V
V
ON
= 0.2V
V
ON
= 0V
Current Sense
V
PS
V
NS
Positive Sense Pin Voltage
Negative Sense Pin Voltage
0.9
0.9
1
1
1.1
1.1
V
V
* Note: V
PS
and V
NS
are matched
* Note: V
PS
and V
NS
are matched
Pulse Width Control Feed Forward Voltage
V
ON
Effective Pulse Width Control Voltage Range
0.2
6.0
V
*
The “*” denotes specifications that apply over the full temperature range (-40°C to +85°C)
2
9/20/2004
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com
HV9906
Pinout
Pin Description
+V
IN
–
This pin is the input to the internal linear regulator.
V
ON
–The
voltage applied to this pin by a resistor voltage divider
from +V
IN
controls the on time (pulse width) of the gate output.
V
DD
–
This pin is the output of the internal linear regulator and the
supply pin for the internal circuits. It must be bypassed with a low
ESR capacitor to provide a low impedance path for the gate drive
and be capable of storing sufficient energy so that the voltage does
not decay below the UVLO threshold during the time when the
input voltage is below the minimum required by the regulator.
AGND –
This pin is the common connection for analog circuits.
GATE –
This pin is the output for driving the gate of an external N-
channel MOSFET.
+Vin
1
8
GATE
Von
2
HV9906
7
PGND
Vdd
3
6
NS
AGND
4
5
PS
PGND –
This is the common connection for the GATE drive circuit.
NS –
This pin is the negative terminal of the differential sense
feedback circuit.
PS –
This pin is the positive terminal of the differential sense
feedback circuit.
__________________________________________________________________________________________________________________
Functional Block Diagram
+Vin
High Voltage
Regulator
UVLO
and
POR
Bandgap
Reference
1V
Vref
Vdd
Von
Vdd
Vdd
Vref
R
_
Q
Q
S
VCO
PGND
Driver
GATE
C
C
AGND
Delay
Reset Pulse
Sample Pulse
Delay
Vdd
1V
1V
NS
PS
3
9/20/2004
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com
HV9906
Functional Description
The HV9906 consists of the following functional blocks:
High Voltage Regulator
Bandgap Reference
Under Voltage Lockout and Power On Reset
Voltage Controlled Oscillator
Feed Forward On Time Control
Differential Sense Circuit and Programmable Reference
Integrator
Sample and Hold VCO Control
Gate Driver
Soft Start
The following sections provide a detailed explanation of each of
these blocks.
High Voltage Regulator
All internal circuits operate from a nominal 10V V
DD
supply
provided by an onboard linear regulator capable of accepting input
voltages up to 400V. This regulator blocks reverse current flow
from V
DD
to +V
IN
, such as in the case when the input voltage is a
full wave rectified sine wave. Therefore, if a sufficiently large
bypass capacitor (>1µF) is connected to V
DD
, the operation of the
circuit can be maintained during the times when the full wave
rectified input voltage is less than the regulated output voltage.
High operating frequency and high input voltage applications will
result in increased power dissipation in the regulator. For these
applications efficiency may be improved by bootstrapping the V
DD
pin if a non-isolated +10V output is available. Supertex’s high
voltage technology allows a very low current regulator, rather than
a shunt, to power the IC. This makes it possible to continuously
operate the IC from the AC line, within thermal limits & without
bootstrapping, in certain applications.
Bandgap Reference
As the regulator turns on and the V
DD
voltage rises, a bandgap
reference is activated to establish the regulation point of the
regulator and provide the required references for the internal
circuits. The references are strictly internal and not available at
any pin of the device.
Under Voltage Lockout and Power On Reset
On initial power application the high input voltage (up to 400V)
linear regulator charges the capacitor connected to V
DD
and seeks
to provide a stable supply for the internal circuitry. Under voltage
lockout (UVLO) holds the voltage controlled oscillator (VCO)
disabled until the V
DD
supply rises above a nominal 8.5V and
power on reset (POR) clamps the capacitors in the sample and
hold and integrator circuits low for a short time thereafter, thus
setting the VCO to its lowest frequency state. The UVLO has a
0.5V hysteresis to prevent false triggering due to ripple on V
DD
.
Voltage Controlled Oscillator
The period of the voltage controlled oscillator (VCO) is determined
by the output of the sample and hold circuit while the feed forward
control from the V
ON
pin provides fast direct control of the oscillator
output on time. For unusual operating circumstance the VCO may
be driven to its maximum frequency and the on time may exceed
the period of the oscillator. This will cause cycle skipping or an
effective reduction in output frequency by an integer factor.
To Least Negative
Sense Node
Relative to +1 Volt
Feed Forward On Time Control
The output signal to the gate driver is controlled by a latch that is
set by the output of the VCO and reset by the feed forward on time
control, thus the voltage applied to the V
ON
pin provides direct and
continuous control of the gate drive on time. The on time is
inversely proportional to the applied voltage and there is an
internally set limit to the maximum on time (17.8µS) so that 0V will
not result in an infinite on time. Refer to “Programming On Time”
in the Design Information section.
To operate in discontinuous conduction mode with constant energy
transfer per cycle a resistor divider from the input voltage is
connected to the V
ON
pin, thereby providing fast feed forward input
regulation control. This control loop can easily track a rectified
sine wave of input voltage at 50Hz, 60Hz or 400Hz provided that
the capacitor connected at V
DD
can store sufficient energy to
prevent decay below the UVLO threshold during the time when the
rectified sine wave input voltage at +V
IN
is below 10V. For a 100V
50Hz rectified sine wave a 3.3µF capacitor connected to V
DD
is
sufficient to guarantee stable operation.
For power factor correction applications an input voltage peak
detector or a low pass filter can be used to drive the V
ON
pin. This
will provide an essentially constant on time control voltage
resulting in an energy transfer per oscillator cycle directly
proportional to the input voltage.
Differential Sense Circuit and Programmable Reference
The following simplified equivalent circuit is provided to clarify the
operation and programming of this circuit.
Vdd
+1V
20pF
PS
R
PS
To Sample and Hold
Comparators
+1V
NS
R
NS
To Most Negative
Sense Node
Relative to +1Volt
This differential sense circuit is typically used to monitor the output
voltage or current of a power converter. The circuit operates by
sourcing current (typically 5µA) from both the PS and NS pins
which are regulated at a nominal +1V and the control loop seeks to
maintain a sense node voltage (voltage across a current sense
resistor or the voltage across a resistor divider) that will make the
NS and PS currents equal. Regulation is established when there
is zero current difference in the PS and NS pins. This differential
common mode sense method reduces noise sensitivity and
enables the user to define the magnitude of the sensed voltage
(i.e. +100mV for high efficiency or –2.5V to escape the noise floor)
and thus the effective reference, provided the sensed nodes are at
less than +1V with respect to ground.
To ensure tight regulation, 10nF ceramic or film capacitors are
needed from PS and NS to ground, respectively. These capacitors
ensure a matched slew rate from supply to supply and further
provide a dominant pole compensation of both transconductors.
4
9/20/2004
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com
HV9906
Functional Description -
continued
The voltage difference between the sensed nodes will require the
selection of resistor values in series with the NS and PS pins that
will result in current balance. While balance can be achieved even
if neither sensed node is at ground potential, care must be taken to
assure that the dynamic voltage excursions of the sensed node
within the design operating range (i.e. 50KHz to 250KHz) of the
particular application does not result in common mode current
swings in the PS and NS pins that would result in saturation of the
integrators.
Saturation at frequencies below the minimum
operating frequency of the application is permitted* since by design
the circuit will soft start from its lowest frequency.
To regulate on a sense node voltage of +0.5V with respect to
ground connect a 200kΩ resistor from the NS pin to the ground
end of the sense element and a 100kΩ resistor from the PS pin to
the +0.5V end of the sense element. Since the voltage drop on the
200kΩ resistor connected to the NS pin is 1V, a reference current
of 5µA is established. To achieve current balance in the PS pin
the sensed node must rise to +0.5V.
For regulating a sense node voltage of –1V with respect to ground
connect a 200kΩ resistor from the PS pin to the ground end of the
sense element and a 400kΩ resistor from the NS pin to the –1V
end of the sense element. Since the voltage drop on the 200kΩ
resistor connected to the PS pin is 1V, a reference current of 5µA
is established. To achieve current balance in the NS pin the
sensed node must fall to -1V.
For calculating the required resistor values refer to “Programming
the Sense Inputs” in the Design Information section.
Integrator
The differential output current of the differential sense circuit is fed
to two matched internal 20pF capacitors that make up the
differential integrator circuit. The tolerances of these integrated
capacitors are typically
±5%,
however, since they are matched,
their absolute values only affect the peak voltage of the integrators.
Operating at the lowest frequency results in the highest peak
voltage on the integrators, which will saturate if the peak voltage
on the capacitors exceeds 6V, resulting in a loss of regulation.
This must be taken into consideration when deciding on the value
of the sense currents in the PS and NS pins. The signals at the
sensed nodes may be discontinuous (i.e. controlling the average
output current into LEDs) since the signals are cycle-averaged by
the differential integrator. The differential output of the integrator is
fed to the sample and hold comparators.
*The circuit soft starts from the lowest frequency, therefore it is
very likely that the integrators will saturate during startup. By
design the VCO frequency will be incremented in the event of a
saturated condition, thereby guaranteeing that the circuit will start.
Sample and Hold VCO Control
The cycle-averaged outputs of the differential integrator are
compared by the window comparator of the sample and hold
circuit. If the differential integrator outputs are unequal the sample
and hold circuit increments or decrements the VCO control voltage
by a fixed small step resulting in a shorter or longer subsequent
VCO cycle and thus an increased or decreased frequency. When
the cycle-averaged signals from the differential integrator are
nearly equal (within the hysteresis band of the comparators) the
sample and hold function is halted and the off time is unchanged.
Since the frequency is incremented or decremented in small fixed
steps at the end of each cycle the rate of frequency increase or
decrease is a function of the frequency and thus the oscillator
frequency will change exponentially.
In this manner the Integrator Lock Loop (IL
2
) feedback controls the
oscillator frequency based on a cycle-averaged sensed value to
maintain output regulation. For certain off-line topologies, the
result is near fixed frequency operation for a fixed load with a
dither of a few KHz which helps in meeting FCC conducted
emission requirements.
Gate Driver
The gate driver buffers the output of the VCO and provides
sufficient gate drive power to achieve rise and fall times below
75nS into a 750pF equivalent MOSFET gate. The under voltage
lockout (UVLO) assures that sufficient voltage is available to drive
the gate of standard or logic level threshold MOSFETs.
Soft Start
On initial power application the UVLO and POR resets the output
latch and sets the VCO to its lowest frequency state, which
represents minimum power transfer per VCO cycle. Thereafter,
the differential sense feedback loop increments the frequency in
small steps, increasing the power transfer rate until output
regulation is achieved, thereby providing the required soft start
function.
5
9/20/2004
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com
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