CoreMP7
Product Summary
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Personal Audio (MP3, WMA, and AAC Players)
Personal Digital Assistants
Wireless Handset
Pagers
Digital Still Camera
Inkjet/Bubble-Jet Printer
Monitors
Verification and Compliance
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Compliant with ARMv4T ISA
Compatible with ARM7TDMI-S
Core Version
•
This Datasheet Defines the Functionality for
CoreMP7 v1.0.
Contents
Introduction ............................................................... 1
Device Utilization ....................................................... 2
General Description ................................................... 3
Programmer’s Model ................................................. 7
AHB Wrapper ........................................................... 12
CoreMP7 Variants ..................................................... 13
Delivery and Deployment ........................................ 14
Bus Functional Model .............................................. 14
AC Parameters .......................................................... 19
Debug ....................................................................... 23
Ordering Information .............................................. 28
List of Changes ......................................................... 28
Datasheet Categories ............................................... 29
Key Features
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FPGA Optimized ARM7™ Family Processor
Compatible with ARM7TDMI-S™
32/16-Bit RISC Architecture (ARMv4T)
32-Bit ARM
®
Instruction Set
16-Bit Thumb
®
Instruction Set
32-Bit Unified Bus Interface
3-Stage Pipeline
32-Bit ALU
32-Bit Memory Addressing Range
Static Operation
EmbeddedICE-RT™ Real-Time Debug Unit
JTAG Interface Unit
Benefits
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Fully Implemented in FPGA Fabric
All Microprocessor I/Os Available to User
Unified Bus Interface Simplifies SoC Design
ARM and Thumb Instruction Sets Can Be Mixed
Introduction
The CoreMP7 soft IP core is an ARM7 family processor
optimized for use in Actel ARM-ready FPGAs and is
compatible with the ARM7TDMI-S. Users should refer to
the
ARM7TDM-S Technical Reference Manual
(DDI0234A-
7TMIS-R4.pdf), published by the ARM Corporation, for
detailed information on the ARM7. The ARM7 TRM is
available for download from the ARM website at
www.arm.com.
CoreMP7 is supplied with an Advanced Microcontroller Bus
Architecture (AMBA) Advanced High-Performance Bus
(AHB) compliant wrapper for inclusion in an AMBA-based
processor system such as the one generated by the Actel
CoreConsole IP Deployment Platform (IDP).
ARM Supported Families
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ProASIC
®
3 (M7A3P)
Fusion (M7AFS)
Synthesis and Simulation Support
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Directly Supported within the Actel Libero
®
Integrated Design Environment (IDE)
Synthesis: Synplify
®
and Design Compiler
®
Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
July 2007
© 2006 Actel Corporation
v 2 .6
1
CoreMP7
ARM7 Family Processor
CoreMP7 is a general purpose, 32-bit, ARM7 family
microprocessor that offers high performance and low
power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles. The
simplicity of RISC results in a high instruction throughput
and fast real-time interrupt response from a small and
cost-effective processor core. Pipeline techniques are
employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one
instruction is being executed, its successor is being
decoded, and a third instruction is being fetched from
memory. The CoreMP7 processor also implements the
Thumb instruction set, which makes it ideally suited to
high-volume applications with memory restrictions, or
applications where code density is an issue.
The 16-bit Thumb instruction set approaches twice the
density of standard ARM code while retaining most of
the ARM performance advantage over a traditional
16-bit processor using 16-bit registers. This is possible
because Thumb code operates on the same 32-bit
register set as ARM code. Thumb code is able to reduce
up to 65% of the code size compared to 32-bit ARM
Table 1 •
Device
Variant
M7A3P1000
Core Only
Core Plus Debug
M7AFS600
Core Only
Core Plus Debug
28.08
20.57
28.12
21.7
CoreMP7 Utilization and Performance
Performance (MHz)
instructions, and offers 160% of the performance of an
equivalent ARM processor connected to a 16-bit memory
system.
Device Utilization
CoreMP7 is available with and without debug for use in
each ARM-enabled device. These variants (Core only or
Core plus debug) are available in CoreConsole and are
easily selected from the core configuration menus. The
utilization and performance of the variants for each
device are shown in
Table 1.
Core Only
This variant of the CoreMP7 is optimized for maximum
speed and minimum size and does not include debug.
Core Plus Debug
This variant of the CoreMP7 is optimized for minimum
size and includes debug.
Tiles
RAM Block
Utilization (%)
6,083
7,931
4
4
24.8%
32.3%
6,083
7,931
4
4
44.0%
57.4%
2
v2.6
CoreMP7
General Description
The CoreMP7 processor architecture, core, and functional diagrams are illustrated in the following figures:
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The CoreMP7 block diagram is shown in
Figure 1.
The CoreMP7 core is shown in
Figure 2 on page 4.
The CoreMP7 functional diagram is shown in
Figure 3 on page 5.
EmbeddedICE-RT
Macrocell
LOCK
WRITE
SIZE[1:0]
PROT[1:0]
TRANS[1:0]
ADDR[31:0]
Databus
WDATA[31:0]
RDATA[31:0]
Scanchain 1
Scanchain 2
DBGRNG(0)
DBGRNG(1)
DBGEXT(0)
DBGEXT(1)
CPU
Coprocessor
Interface Signals
EmbeddedICE-RT
TAP Controller
DBGTCKEN
DBGTMS
DBGnTRST
DBGTDI
DBGTDO
Figure 1 •
CoreMP7 Top-Level Block Diagram
v2.6
3
CoreMP7
ADDR[31:0]
Address Register
PC Bus
Address
Incrementer
Incrementer Bus
Register Bank
CLK
CLKEN
CFGBIGEND
nIRQ
nFIQ
nRESET
ABORT
Instruction
Decoder and
Control Logic
B Bus
LOCK
WRITE
SIZE[1:0]
PROT[1:0]
TRANS[1:0]
DBG Outputs
DBG Input
CP Control
CP Handshake
ALU Bus
Multiplier
A Bus
Shifter
ALU
Write Data Register
Instruction Pipeline
Read Data Register
Thumb Instruction Decoder
WDATA[31:0]
RDATA[31:0]
Figure 2 •
CoreMP7 CPU Block Diagram
4
v2.6
CoreMP7
DBGTCKEN
CLK
Clock
CLKEN
nIRQ
Interrupts
nFIQ
nRESET
CFGBIGEND
DBGTMS
DBGTDI
DBGnTRST
DBGTDO
DBGnTDOEN
ADDR[31:0]
WDATA[31:0]
RDATA[31:0]
DMORE
Arbitration
LOCK
DBGINSTRVALID
DBGRQ
DBGBREAK
DBGACK
DBGnEXEC
DBGEXT[1]
Debug
DBGEXT[0]
DBGEN
DBGRNG[1]
DBGRNG[0]
DBGCOMMRX
DBGCOMMTX
CPnMREQ
CPSEQ
CPTBIT
CPnl
CPA
CPB
Coprocessor
Interface
CPnTRANS
CPnOPC
Memory
Management
Interface
CoreARM7
ABORT
WRITE
SIZE[1:0]
PROT[1:0]
TRANS[1:0]
Memory
Interface
Synchronized
EmbeddedICE-RT
Scan Debug
Access Port
Bus Control
Figure 3 •
CoreMP7 Functional Diagram
The signals of the CoreMP7 are listed in
Table 2.
Table 2 •
Name
ABORT
CFGBIGEND
CLK
CLKEN
CPA
CPB
DBGBREAK
DBGEN
DBGEXT[1:0]
Signal Descriptions
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Memory abort or bus error
Big/Little Endian configuration
Clock
Clock enable
Coprocessor absent
Coprocessor busy
EICE breakpoint/watchband indicator
Debug enable
EICE external input 0
Description
Note:
The CoreMP7 is available with either the native ARM7 bus interface or with an AHB wrapper. The use of the AHB wrapper changes
or transforms some of the signals in
Table 2.
This is discussed in detail later in this document.
v2.6
5
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