HV310
Hotswap, Inrush Current Limiter Controllers
(Negative Supply Rail)
Features
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PWRGD = Active Low
-10V to -90V input voltage range
Few external components
0.33mA typical standby supply current
Programmable over/under voltage limits with
hysteresis
Programmable current limit
Active control during all phases of start-up
Programmable timing
8-Lead SOIC package
General Description
The Supertex HV310, Hotswap Controller, Negative Supply controls the power
supply connection during insertion of cards or modules into live backplanes.
It may be used in traditional ‘negative 48V’ powered systems or for higher
voltage busses up to negative 90V.
Operation during the initial power up prevents turn-on glitches, and after
complete charging of load capacitors (typically found in filters at the input
of DC-DC converters) the HV310 issues a power good signal. This signal is
typically used to enable the DC-DC converter. Once a PWRGD signal has
been established, the device sleeps in a low power state, important for large
systems with many individual hotswap cards or modules.
An external power MOSFET is required as the pass element, plus a ramp
capacitor, and resistors to establish current limiting and over and under voltage
lockouts. There is no need for additional external snubber components.
Features are programmable over voltage and under voltage detection of the
input voltage which locks out the load connection if the bus (input) voltage
is out of range. An internal voltage regulator creates a stable reference,
and maintains accurate gate drive voltage. The unique control loop scheme
provides full current control and limiting during start up.
Applications
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Central office switching
Servers
POTS line cards
ISDN line cards
xDSL line cards
PBX Systems
Powered Ethernet for VoIP
Distributed power systems
Negative power supply control
Antenna and fixed wireless systems
Theory of Operation
Initially the external N-channel MOSFET is held off by the gate signal,
preventing an input glitch. After a delay (while internal circuits are activated)
the inrush current to the load is limited by the gate control output. The current
may ramp up and limit at a maximum value programmed by an external
resistor. Initial time delay, to allow for contact bounce, and charging operation
is determined by the single external ramp capacitor connected to the RAMP
pin. When the load capacitor is fully charged, the controller emerges from
current limit mode, an additional time delay occurs before the external N-
channel MOSFET pass transistor is switched to full conduction, and the
PWRGD output signal is activated. The controller will then transition to a low
power standby mode.
Typical Application Circuit
GND
Long Pin
Jumper
8
GND
Short Pin
VDD
PWRGD
R1
487kΩ
R2
6.81kΩ
R3
9.76kΩ
1
ENABLE
3
UV
HV310
+5V
2
C
LOAD
OV
RAMP
DC/DC
PWM
CONVERTER
COM
VEE
4
SENSE
5
GATE
6
NOTES:
1. Undervoltage Shutdown (UV) set to 35V.
2. Overvoltage Shutdown (OV) set to 65V.
3. Remove jumper if short pin is used.
-48V
Long Pin
C1
10nF
7
R4
50mΩ
Q1
IRF530
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV310
Ordering Information
Package Option
Device
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
8-Lead SOIC
HV310
HV310LG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
EE
referenced to VDD pin
V
PWRGD
referenced to V
EE
voltage
Operating ambient temperature
Operating junction temperature
Storage temperature
UV and OV referenced to V
EE
Value
+0.3 to -100V
-0.3 to +100V
-40°C to +85°C
-40°C to +125°C
-65°C to +150°C
-0.3 to +12V
Pin Configuration
PWRGD
OV
UV
VEE
1
2
3
4
8
7
6
5
VDD
RAMP
GATE
SENSE
8-Lead SOIC (LG)
(top view)
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Product Marking
HV310
YWW
LLLL
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead SOIC (LG)
Electrical Characteristics
(V
Sym
Supply
V
EE
I
EE
Parameter
(Referenced to VDD pin)
IN
= -10 to -90V, -40°C ≤ T
A
≤ +85°C unless otherwise noted)
Min
-90
-
-
-
-
-
-
-
-
Typ
-
550
330
1.26
1.16
100
1.26
1.16
100
Max
-10
650
400
-
-
-
-
-
-
Units
V
µA
µA
V
V
mV
V
V
mV
Conditions
---
V
EE
= -48V, mode = limiting
V
EE
= -48V, mode = standby
Low to high transition
High to low transition
---
Low to high transition
High to low transition
---
Supply voltage
Supply current
Standby mode supply current
(Referenced to VEE pin)
OV and UV Control
V
UVH
V
UVL
V
UVHY
V
OVH
V
OVL
V
OVHY
UV high threshold
UV low threshold
UV hysteresis
OV high threshold
OV low threshold
OV hysteresis
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV310
Electrical Characteristics
(V
Sym
V
SENSE
V
GATE
I
GATEUP
I
GATEDOWN
I
RAMP
t
POR
t
RISE
t
LIMIT
t
PWRGD
V
RAMP
Parameter
(Referenced to VEE pin)
IN
= -10 to -90V, -40°C ≤ T
A
≤ +85°C unless otherwise noted)
Min
40
9.0
500
40
-
2.0
400
-
-
-
90
-
-
-
Typ
50
10
-
-
10
-
-
-
5.0
3.6
-
0.5
-
-
Max
60
11
-
-
-
-
-
5.0
-
-
-
0.8
500
500
Units
mV
V
µA
mA
µA
ms
µs
ms
ms
V
V
V
ns
ns
Conditions
V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V
V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V
V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V
V
UV
= V
EE
, V
OV
= V
EE
+ 0.5V
V
SENSE
= 0V
---
---
---
---
---
---
I
PWRGD
= 1.0mA
---
---
Current Limit
Current limit threshold voltage
Maximum GATE drive voltage
GATE drive pull-up current
GATE drive pull-down current
Ramp pin output current
Time from UV to GATE turn on
1
Time from GATE turn on to V
SENSE
limit
Duration of current limit mode
Time from current limit to PWRGD
Voltage on ramp pin in current limit mode
2
Power good pin breakdown voltage
Power good pin output low voltage
OV delay
UV delay
Gate Drive Output
(Referenced to VEE pin)
Timing Control
(Test Conditions: C =100µF, C
RAMP
= 10nF, V
UV
= V
EE
+1.9V, V
OV
= V
EE
+0.5V, External MOSFET is IRF530
3
)
Power Good Output
(Referenced to VEE pin)
V
PWRGD
Dynamic Characteristics
t
GATEHLOV
t
GATEHLUV
Notes
1. This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
2. This voltage depends on the characteristics of the external N-Channel MOSFET. V
GS(th)
= 3.0V for an IRF530.
3. IRF530 is a registered trademark of International Rectifier.
PWRGD Logic
Device
HV310
Condition
Not Ready
Ready
1
0
PWRGD
Hi Z
V
EE
Waveforms
Drain
50V/div
V
IN
50V/div
GATE
5.0V/div
I
INRUSH
500mA/div
5.0ms/div
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV310
Timing Diagram
contact
bounce
GND
I
LIM
=
V
OUT
V
SENSE
R
SENSE
C
RAMP
I
RAMP
V
OUT
-48V
V
IN
V
UVL
V
IN
t
START
= 12V
V
GATE
t
START
t
TH
= V
GS(th)
C
RAMP
I
RAMP
V
RAMP
V
GATE
V
EE
V
RAMP
V
GS(th)
V
GATE
V
GS(lim)
t
POR
= t
START
+ t
TH
t
RISE
≈
g
fs
C
RAMP
I
RAMP
0.9I
LIM
C
LOAD
I
LIM
-
-
1
2
R
SENSE
R
FB
t
RISE
C
RAMP
I
RAMP
t
TH
I
IN
t
POR
I
LIM
t
RISE
active
t
PWRGD
t
LIM
t
LIM
≈ V
IN
PWRGD
inactive
Initialization
Limiting
Full On
t
PWRGD
= (V
INT
- V
GS(LIM)
- 1.2V)
Note:
1. V
INT
is the internally regulated supply voltage and can range from 9.0 to 11V.
2. V
GS(th)
is the gate threshold voltage of the external pass transistor and may be obtained from its datasheet.
3. V
GS(lim)
is the pass transistor gate-source voltage required to obtain the limit curent. It is dependent on the pass transistor’s characteristics and may
be obtained from the transfer characteristics curves on the transistor datasheet.
4. g
fs
is the transconductance of the pass transistor and may be obtained from its datasheet.
5. R
FB
is the internal feedback resistor and is 5.0kΩ nominal.
Functional Block Diagram
VDD
Internal
Supply
Regulator
Band Gap
Reference
V
REF
UVLO
and
POR
V
INT
PWRGD
C
UV
V
REF
C
Automatic
Restart
Delay
LOGIC
OV
V
INT
10mA
C
2V
REF
Transconductor
-
V
INT
- 1.2V
Switch
A
+
Circuit
Breaker
C
100mV
Buffer
5kΩ
VEE
SENSE
RAMP
GATE
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
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Tel: 408-222-8888
●
www.supertex.com
4
HV310
Functional Description
Insertion Into Hot Backplanes
Telecom, Data Network and some computer applications
require the ability to insert and remove circuit cards from
systems without powering down the entire system. All cir-
cuit cards have some filter capacitance on the power rails,
which is especially true in circuit cards or network terminal
equipment utilizing distributed power systems. The insertion
can result in high inrush currents that can cause damage to
connector and circuit cards and may result in unacceptable
disturbances on the system backplane power rails.
The HV310 was designed to allow the insertion of these cir-
cuit cards or connection of terminal equipment by eliminat-
ing these inrush currents and powering up these circuits in
a controlled manner after full connector insertion has been
achieved. The HV310 is intended to provide this function on
a negative supply rail in the range of -10 to -90V.
Operation
On initial power application an internal regulator seeks to pro-
vide 10V for the internal IC circuitry. Until the proper internal
voltage is achieved all circuits are held reset, the open drain
PWRGD signal is Hi-Z to inhibit the start of any load circuitry
and the gate to source voltage of the external N-channel
MOSFET is held low. Once the internal under voltage lock
out (UVLO) has been satisfied, the circuit checks the input
supply voltage under voltage (UV) and over voltage (OV)
sense circuits to ensure that the input voltage is within ac-
ceptable programmed limits. These limits are determined by
the selected values of resistors R1, R2 and R3, which form
a voltage divider.
Assuming the above conditions are satisfied and while con-
tinuing to hold the PWRGD output inactive and the external
MOSFET GATE voltage low, the current source feeding the
RAMP pin is turned on. The external capacitor connected to
it begins to charge, thus starting an initial time delay deter-
mined by the value of the capacitor. If an interruption of the
input power occurs during this time (i.e. caused by contact
bounce) or the OV or UV limits are exceeded, an immedi-
ate reset occurs and the external capacitor connected to the
RAMP pin is discharged.
When the voltage on the RAMP pin reaches an internally
set voltage limit, the gate drive circuitry begins to turn on the
external MOSFET; allowing the current to softly rise over a
period of a few hundred micro-seconds to the current limit
set point. While the circuit is limiting current, the voltage on
the RAMP pin will be fixed.
Depending on the value of the load capacitance and the
programmed current limit, charging may continue for some
time. The magnitude of the current limit is programmed by
comparing a voltage developed by a sense resistor connect-
ed between the VEE and SENSE pins to 50mV (Typical).
Once the load capacitor has been charged, the current will
drop which will cause the ramp voltage to continue rising;
providing yet another programmed delay.
When the ramp voltage is within 1.2V of the internally regu-
lated voltage, the controller will force the GATE full on and
will pull the PWRGD pin low and the circuit will transition to a
low power standby mode. The PWRGD pin is often used as
an enable for downstream DC/DC converter loads.
At any time during the start up cycle or thereafter, crossing
the UV and OV limits (including hysteresis) will cause an im-
mediate reset of all internal circuitry. Thereafter the start up
process will begin again.
Application Information
Under Voltage and Over Voltage Detection
The UV and OV pins are connected to comparators with
nominal 1.21V thresholds and 100mV of hysteresis (1.21V
± 50mV). They are used to detect under voltage and over
voltage conditions at the input to the circuit. Whenever the
OV pin rises above its threshold or the UV pin falls below its
threshold the GATE voltage is immediately pulled low, the
PWRGD signal is deactivated and the external capacitor
connected to the RAMP pin is discharged.
The under voltage and over voltage trip points can be pro-
grammed by means of the three resistor divider formed by
R1, R2 and R3. Since the input currents on the UV and OV
pins are negligible the resistor values may be calculated as
follows:
UV
OFF
= V
UVH
= 1.16 = |V
EEUV
| • (R2+R3) / (R1+R2+R3)
OV
OFF
= V
OVL
= 1.26 = |V
EEOV
| • R3 / (R1+R2+R3)
Where |V
EEUV
| and |V
EEOV
| are Under & Over Voltage Set
points.
If we select a divider current of 100µA at a nominal operating
input voltage of 50V then:
(R1+R2+R3) = 50V / 100µA = 500kΩ
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
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Tel: 408-222-8888
●
www.supertex.com
5
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