= +3.3 V; applies to each ADC unless otherwise noted.)
Test
Level
Mil
Subgroup
Min
AD10265AZ
Typ
12
Guaranteed
+3.5
±
0.5
±
0.8
±
0.2
0.2
Max
Unit
Bits
Temp
–10
–1.5
–2.5
+10
+1.5
+2.5
0.5
mV
% FS
% FS
%
dB
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
V
V
V
IV
IV
IV
IV
V
V
IV
IV
IV
IV
IV
IV
VI
IV
V
V
V
IV
IV
IV
I
II
I
II
I
II
I
II
I
II
I
II
12
12
12
12
99
198
396
0
±
0.5
±
1.0
±
2
100
200
400
4.0
160
50
TTL/CMOS
2.0
0
500
–400
12
4, 5, 6
12
65
6.5
400
±
2.0
0.3
12
12
12
4
5, 6
4
5, 6
4
5, 6
4
5, 6
4
5, 6
4
5, 6
6.5
6.5
7.0
62
60.5
61
60
61
59.5
61
60
61
59.5
61
59
5.0
0.8
800
–200
7.0
101
202
404
7.0
V
V
V
Ω
Ω
Ω
pF
MHz
kHz
Full
Full
Full
Full
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
650
–320
4.5
V
V
µA
µA
pF
MSPS
MSPS
ps
ns
ps rms
ns
ns
ns
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
9.0
66
66
65
65
63
62
65
64
64
63
62
62
12.5
–2–
REV. A
AD10265
Parameter
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 1.24 MHz
@ 17 MHz
@ 32 MHz
TWO-TONE IMD REJECTION
10
f1, f2 @ –7 dBFS
CHANNEL-TO-CHANNEL ISOLATION
11
LINEARITY
Differential Nonlinearity
(Encode = 20 MHz)
Integral Nonlinearity
(Encode = 20 MHz)
DIGITAL OUTPUTS
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Output Coding
POWER SUPPLY
AV
CC
Supply Voltage
I (AV
CC
) Current
AV
EE
Supply Voltage
I (AV
EE
) Current
DV
CC
Supply Voltage
I (DV
CC
) Current
I
CC
(Total) Supply Current
Power Dissipation (Total)
Power Supply Rejection Ratio (PSRR)
Temp
25°C
Full
25°C
Full
25°C
Full
Full
25°C
Test
Level
I
II
I
II
V
V
V
IV
Mil
Subgroup
4
5, 6
4
5, 6
Min
75
74
71
70
AD10265AZ
Typ
80
80
80
79
79
79
77
Max
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dB
4, 5, 6
12
66
80
25°C
Full
IV
V
12
–1.0
±
0.5
±
1.25
+1.5
LSB
LSB
Full
Full
I
I
1, 2, 3
1, 2, 3
CMOS
2.8
DV
CC
– 0.2
0.2
0.5
Two’s Complement
+5.0
336
–5.0
66
+3.3
20
422
2.1
0.01
V
V
Full
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
I
I
IV
1, 2, 3
1, 2, 3
12
520
2.4
0.02
V
mA
V
mA
V
mA
mA
W
% FSR/% V
S
NOTES
1
Gain tests are performed on A
IN
1 over specified input voltage range.
2
Input capacitance specifications show only ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
ENCODE driven by single-ended source;
ENCODE
bypassed to ground through 0.01
µF
capacitor.
5
ENCODE may also be driven differentially in conjunction with
ENCODE;
see “Encoding the AD10265” for details.
6
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%
±
5%.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.
9
Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 17.0 MHz
±
100 kHz, f2 = 18.0 MHz
±
100 kHz.
11
Channel-to-channel isolation tested with A channel/50 ohm terminated <A
IN
2 grounded, and a full-scale signal applied to B channel (A
IN
1).
All specifications guaranteed within 100 ms of initial power-up, regardless of sequencing.
Specifications subject to change without notice.
REV. A
–3–
AD10265
ABSOLUTE MAXIMUM RATINGS
1
Parameter
ELECTRICAL
V
CC
Voltage
V
EE
Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage (ENCODE)
ENCODE,
ENCODE
Differential Voltage
Digital Output Current
ENVIRONMENTAL
Operating Temperature (Case)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
2
Table I. Output Coding
Min
0
–7
V
EE
–10
0
–10
–55
Max
+7
0
V
CC
+10
AV
CC
4
+10
+125
175
300
+150
Unit
V
V
V
mA
V
V
mA
°C
°C
°C
°C
MSB
LSB
Base 10
2047
+1
0
–1
2048
Input
+FS
0.0 V
–FS
0111111111111
0000000000001
0000000000000
1111111111111
1000000000000
EXPLANATION OF TEST LEVELS
Test Level
I.
100% production tested.
II. 100% production tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample tested only.
IV. Parameter is guaranteed by design and characteriza-
tion testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at 25°C; sample
tested at temperature extremes.
–65
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances for “Z” package:
θ
JC
= 11°C/W;
θ
JA
= 30°C/W.
ORDERING GUIDE
M
odel
Temperature Range
–25°C to +85°C (Case)
+25°C
–25°C to +125°C (Case)
–25°C to +125°C (Case)
Package Description
68-Lead Ceramic Leaded Chip Carrier
Evaluation Board with AD10265AZ
68-Lead Ceramic Leaded Chip Carrier
68-Lead Ceramic Leaded Chip Carrier
Package Option
ES-68C
ES-68C
ES-68C
AD10265AZ
AD10265/PCB
5962-9865901 HXA
5962R0151901 TXA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD10265 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD10265
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2, 5, 9–11, 26, 27
3, 4, 12, 15, 16,
34, 35, 55–57
6
7
8
13
14
17–25, 31–33
28
29
30
36–42, 45–49
43, 44, 53, 54,
58–61, 65, 68
50
51
52
62
63
64
66
67
Name
SHIELD
GNDA
NC
A
IN
A1
A
IN
A2
A
IN
A3
AV
EE
AV
CC
D0A–D11A
ENCODEA
ENCODEA
DV
CC
D0B–D11B
GNDB
DV
CC
ENCODEB
ENCODEB
A
IN
B1
A
IN
B2
A
IN
B3
AV
CC
AV
EE
Function
Internal Ground Shield between channels.
A Channel Ground. A and B grounds should be connected as close to the device as possible.
No Connect. Pins 15 and 16 are internal test pins: it is recommended to connect
them to GND.
Analog Input for A side ADC (nominally
±
0.5 V).
Analog Input for A side ADC (nominally
±
1.0 V).
Analog Input for A side ADC (nominally
±
2.0 V).
Analog Negative Supply Voltage (nominally –5.0 V). For A side ADC.
Analog Positive Supply Voltage (nominally +5.0 V). For A side ADC.
Digital Outputs for ADC A. D0 (LSB).
ENCODE
is complement of ENCODE.
Data conversion initiated on rising edge of ENCODE input.
Digital positive supply voltage (nominally 3.3 V) for A side ADC.
Digital Outputs for ADC B. D0 (LSB).
B Channel Ground. A and B grounds should be connected as close to the device
as possible.
Digital Positive Supply Voltage (nominally 3.3 V) for B side ADC.
Data conversion initiated on rising edge of
ENCODE
input.
ENCODE
is complement of ENCODE.
Analog Input for B side ADC (nominally
±
0.5 V).
Analog Input for B side ADC (nominally
±
1.0 V).
Analog Input for B side ADC (nominally
±
2.0 V).
Analog Positive Supply Voltage (nominally +5.0 V). For B side ADC.
Analog Negative Supply Voltage (nominally –5.0 V). For B side ADC.
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