DISCRETE SEMICONDUCTORS
DATA SHEET
dbook, halfpage
MBD128
BGA2011
900 MHz high linear low noise
amplifier
Product specification
Supersedes data of 2000 Sep 06
2000 Dec 04
NXP Semiconductors
Product specification
900 MHz high linear low noise amplifier
FEATURES
Low current, low voltage
High linearity
High power gain
Low noise
Integrated temperature compensated biasing
Control pin for adjustment bias current.
APPLICATIONS
RF front end
Low noise amplifiers, e.g. CDMA, PHs, Dect, etc.
DESCRIPTION
Silicon Monolitic Microwave Integrated Circuit (MMIC)
amplifier consisting of an NPN double polysilicon transistor
with integrated biasing for low voltage applications in a
6-pin SOT363 plastic SMD package.
handbook, halfpage
BGA2011
PINNING
PIN
1
2
3
4
5, 6
RF in
V
C
V
S
RF out
GND
DESCRIPTION
VS
5
4
6
RF out
VC
1
2
3
MBL251
BIAS
CIRCUIT
Top view
RF in
GND
Marking code:A5-
Fig.1 Simplified outline (SOT363) and symbol.
QUICK REFERENCE DATA
SYMBOL
V
S
I
S
I
C
|s
21
|
2
NF
PARAMETER
DC supply voltage
DC supply current
DC control current
insertion power gain
noise figure
V
C
= V
S
in application circuit, see Fig.2;
f = 900 MHz
I
S
= 15 mA; f = 900 MHz
CONDITIONS
RF input AC coupled
3
15
0.11
19
1.7
TYP.
MAX.
4.5
UNIT
V
mA
mA
dB
dB
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134)
SYMBOL
V
S
V
C
I
S
I
C
P
tot
T
stg
T
j
PARAMETER
DC supply voltage
voltage on control pin
supply current
control current
total power dissipation
storage temperature
operating junction temperature
T
s
100
C
forced by DC voltage on RF input
CONDITIONS
RF input AC coupled
65
MIN.
MAX.
4.5
V
S
30
0.25
135
+150
150
UNIT
V
V
mA
mA
mW
C
C
2000 Dec 04
2
NXP Semiconductors
Product specification
900 MHz high linear low noise amplifier
THERMAL CHARACTERISTICS
SYMBOL
R
th j-s
PARAMETER
thermal resistance from junction
to solder point
CONDITIONS
P
tot
= 135 mW; T
s
100
C
VALUE
350
BGA2011
UNIT
K/W
CHARACTERISTICS
RF input AC coupled; V
S
= 3 V; I
S
= 15 mA; f = 900 MHz; T
j
= 25
C;
unless otherwise specified.
SYMBOL
I
S
I
C
R
L IN
PARAMETER
supply current
control current
return losses input
typical application; see Fig.2
high IP3 (see Fig.2; stripline = 0 mm)
high IP3 (see Fig.2; stripline = 1.5 mm)
R
L OUT
return losses output
typical application; see Fig.2
high IP3 (see Fig.2; stripline = 0 mm)
high IP3 (see Fig.2; stripline = 1.5 mm)
|s
21
|
2
insertion power gain
typical application; see Fig.2
high IP3 (see Fig.2; stripline = 0 mm)
high IP3 (see Fig.2; stripline = 1.5 mm)
NF
noise figure
typical application; see Fig.2;
I
S
= 15 mA
high IP3 (see Fig.2; stripline = 0 mm)
high IP3 (see Fig.2; stripline = 1.5 mm)
IP3
in
input intercept point
typical application; see Fig.2
high IP3 (see Fig.2; stripline = 0 mm)
high IP3 (see Fig.2; stripline = 1.5 mm)
CONDITIONS
MIN.
10
TYP.
15
0.11
11
11
17
11
12
14
15
19
16
1.5
1.6
1.7
2
4
10
MAX.
20
UNIT
mA
mA
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
2000 Dec 04
3
NXP Semiconductors
Product specification
900 MHz high linear low noise amplifier
APPLICATION INFORMATION
BGA2011
handbook, full pagewidth
VS
VC
VC
C5
BIAS
CIRCUIT
VS
C4
L2
C2
C3
C1
RF in
IN
L1
C6
stripline
SOT363
OUT
RF out
MLD480
GND
Fig.2 Application circuit.
List of components (see Fig.2)
COMPONENT
C1, C2
C3, C5
C4
C6
L1
L2
Note
1. The stripline (w = 0.7 mm) is on a gold plated double copper-clad printed-circuit board (
r
= 6.15),
board thickness = 0.64 mm, copper thickness = 35
m,
gold thickness = 5
m.
DESCRIPTION
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
SMD inductor
SMD inductor
TYPICAL
APPLICATION
100 pF
22 nF
5.6 pF
HIGH IP3
APPLICATION
100 pF
22 nF
5.6 pF
2 x 100 nF
10 nH
8.2 nH
DIMENSIONS
0603
0603
0603
0805
0603
0603
2000 Dec 04
4
NXP Semiconductors
Product specification
900 MHz high linear low noise amplifier
BGA2011
handbook, halfpage
30
MLD481
handbook, halfpage
20
MLD482
20
IS
(mA)
gain
(dB)
20
gain
(dB)
15
s21
2
IS
15
Gmax
10
10
IS
s21
2
10
5
5
0
0
1000
2000
f (MHz)
3000
0
0
1
2
VC (V)
3
0
I
C
= 15 mA; V
S
= V
C
= 3 V; P
D
=
30
dBm; Z
o
= 50
f = 900 MHz; V
S
= 3 V; P
D
=
30
dBm.
Fig.3
Insertion gain (s
21
2
) and G
max
as
functions of frequency; typical values.
Fig.4
Insertion gain and supply current as
functions of control voltage; typical values.
handbook, halfpage
s
2
20
MLD483
handbook, halfpage
15
MLD484
0
IP3in
(dBm)
−5
21
(dB)
IP3out
(dBm)
10
15
IP3in
10
IP3out
5
5
−10
0
10
−3
10
−2
IC (mA)
10
−1
0
5
10
IS (mA)
−15
15
V
S
= V
C
= 3 V; P
D
=
30
dBm (both tones); f = 900 MHz;
f
= 100 kHz.
f = 900 MHz; V
S
= 4 V; P
D
=
30
dBm.
Fig.6
Fig.5
Insertion gain as a function of control
current; typical values.
Output and input 3rd order intercept point
as a function of supply current;
typical application; typical values.
2000 Dec 04
5
FPGA/CPLD
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