IXYS
Features:
MX8682
12-Bit Digital Output Magnetic Flux Sensor
±100 Gauss / 2KHz Conversion Rate
General Description
The MX8682 is a 12 Bit Digital Output Magnetic
Flux Sensor. The device is a complete sampled
data subsystem that converts a magnetic flux
intensity of ±100 Gauss full scale into a 12-bit digital
output word. The sensor operates as a slave on the
serial interface with TTL-level compatible inputs SDI
(serial data input), SCK (serial clock), and CS* (chip
select, active low). Terminal SDO is the tri-state
serial data output.
An adjustable exponentially weighted moving
average digital filter is included that is capable of
improving the signal to noise ratio while reducing
the signal bandwidth. The full scale trim and/or the
digital filter time constant are controllable through
the serial I/O interface and are one-time
programmable through the serial interface (once
programmed, the values are loaded at every power-
on).
The MX8682 can be mounted onto a PCB or
incorporated into a magnetic assembly and then
calibrated in-system through the serial interface.
The operating voltage range is 4.5V to 5.5V.
•
Higher Sensitivity Version of the MX8681
•
Single 5 Volt Power Supply
•
Externally Configurable ±10A Bi-Direction
Current Sense per Turn
•
12-Bit Serial Digital Output
•
Full Scale Magnetic Flux Intensity of ±100
Gauss
•
2K Conversions/Second
•
Microcontroller Compatible
•
Standard 3 Wire Serial Interface plus Chip
Select
•
In System Calibration: OTP Full Scale Trim via
the Serial I/O Port
•
Programmable Digital Filter Time Constant
•
4mm x 4mm 8 Lead DFN package RoHS
Compliant
Applications:
•
Load Detection and Management
•
Motor Control
•
Power Supplies
Ordering Information
Part No.
Description
MX8682R
DFN-8 Tube
MX8682RTR DFN-8 Tape & Reel
Qty
91
2500
Functional Block Diagram Typical
Power
Application Circuit
PWR
SDI
SCK
Hall
Plate
I/O Reg
SDO
Microcontroller
1
PWR
MISO
Select
MOSI
SCK
2
8
5
4
SDO
CS*
MX8682
SDI
SCK
GND
7
CS*
A/D
GND
Ground
MX8682
Drawing No. 0868209
1
03/03/08
www.claremicronix.com
MX8682
Absolute Maximum Ratings
T
A
= +25°C unless otherwise noted
Parameter
Voltage (Any Pin to GND)
θ
JA
, DFN-8 Package
Operating Temperature Range
Storage Temperature Range
Min
Max
+7
30
+85
150
Unit
V
°C/W
°C
°C
IXYS
-40
-65
ESD Warning
ESD (electrostatic discharge) sensitive device. Although the MX8681 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Electrical Characteristics
PWR= 5V, T = +25°C
Parameter
Operating Voltage Range (PWR)
Supply Current (I
PWR
)
Average A/D Reading
Average A/D Reading
Output Noise
SCK pulse period
SCK pulse width
CS* pulse period
CS* falling to first SCK rising
Last SCK falling to CS* rising
SCK falling to SDO valid
Digital output high
Digital output low
Digital input low
Digital input high
Digital input current
Condition
Min
4.5
2040
Typ
3
2048
3072
5.5
Max
5.5
2056
Zero Magnetic Flux
50 Gauss, North Pole
Digital Filter Off
high or low
5
200
500
100
50
60
PWR-0.5
GND
2
0.5
0.8
PWR
1
Unit
V
mA
LSB
LSB
RMS
LSB
µS
nS
µS
nS
nS
nS
V
V
µA
MX8682
Drawing No. 0868209
2
03/03/08
www.claremicronix.com
MX8682
Pin Description
Pin No.
1
2
3
4
5
6
7
8
Name
PWR
SDO
NC
SCK
SDI
NC
GND
CS*
IXYS
Description
Input Voltage Supply
Serial Data Output
No Connect
Serial Clock Input
Serial Data Input
No Connect
Connect to Ground
Active low chip select for the serial interface. When a logic “high” is on this pin, the
MX8682 is tracking the hall input signal.
Detailed Circuit Description
The hall plate senses the magnetic field that is applied normal (perpendicular) to the package surface.
The signal from the hall plate is offset-corrected by detecting the difference between a pair of analog
samples during the acquisition time. During idle time (CS* high) the MX8682 tracks the first analog
sample. Immediately (~10 nS) after the falling edge of CS* the first sample is held. The track mode for
the second sample starts nominally 32 µS after the falling edge of CS*. Typically 96 µS after the falling
edge of CS* the second sample is held and the resulting analog value is then converted by the A/D. The
result of the A/D conversion is loaded into the I/O register at the next falling edge of CS*, in preparation
for output on SDO.
The internal acquisition and A/D timing is asynchronous to the SCK serial interface clock. The magnetic
field sampling period is controlled externally by the time between consecutive CS* falling edges. For zero
magnetic field input the nominal A/D output is 2048 decimal. North pole towards the top surface of the
MX8682 increases the A/D output count. Applications that require non-continuous one measurement at a
time operation should pulse CS* low twice, reading the data when CS* is low for the second time.
Acquisition (n+1)
Acquisition (n)
CS*
SCK
SDO
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
A/D Convert (n+1)
Serial Output (n)
A/D Convert (n)
externally controlled sampling period
MX8682
Drawing No. 0868209
3
03/03/08
www.claremicronix.com
MX8682
POWER-ON RESET
IXYS
The MX8682 contains a power-on reset circuit that resets all the internal flip-flops and initializes the
internal registers to zero. The MX8682 will reset if the voltage at terminal PWR drops below 3.2V to 3.8V.
SYNCHRONOUS SERIAL I/O
The MX8682 (slave) can communicate with a microcomputer (master) via a three wire plus chip select
serial interface. Chip select CS*, serial clock SCK, and serial data input SDI are output from the master
controller to the MX8682.
Serial data output SDO is driven by the MX8682 when selected by CS* = 0.
SDO is high impedance when CS* = 1.
SCK and SDI are don't care when CS* = 1.
SDI is captured by the rising edge of SCK.
SDO changes in response to the falling edge of SCK.
Read 12-bit data D[11:0] when SDI = logic 0
200 nS min
CS*
SCK
SDI
SDO
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
60 nS max
Write command timing:
(Bit Field A[2:0] , B[5:0], OTP Bit Zp)
20 nS min
CS*
SCK
SDI
1
0
A2
A1
A0
B5
B4
B3
B2
B1
B0
Zp
The write command SDI input bit pattern is internally latched at the rising edge of
CS* and takes effect at the end of the next A/D conversion following CS* rising.
The exponentially weighted moving average digital filter has a transfer function equivalent to a first order
low pass filter.
The I/O timing remains exactly the same when the filter is used. No decimation is performed.
Let T = Sample interval (the time from CS* falling edge to CS* falling edge). Then bandwidth = 1/(2*pi*T).
Also if W = Sample weighting, then the digital output = W*(current sample) + (1-W)*(previous value).
At power-on the previous value is initialized to zero. A programmed change in A[2:0] does not reset the
previous value. Therefore when using the filter, multiple samples must be taken at power-on or after
changing A[2:0] before the filtered output will be correct.
MX8682
Drawing No. 0868209
4
03/03/08
www.claremicronix.com
MX8682
Bit field A[2:0] controls the digital filter operation:
A[2:0]
000
001
010
011
100
101
110
111
Time Constant
No Filter
T
3T
7T
15T
31T
63T
127T
IXYS
Sample Weighting
1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Bit field B[5:0] is the full scale adjust.
Characteristics are 0.8% step size, ±25% total range.
B[5:0] = 000000 is the lowest sensitivity (highest full scale)
B[5:0] = 111111 is the highest sensitivity
One-Time Programming:
Bit Zp, when logic 1 along with A[2:0] and B[5:0] values, programs those values into the internal non-
volatile memory.
Programming a bit to logic 1 is permanent. A bit programmed to logic 1 cannot be made to go back to
logic 0.
Always send a write command with Zp = 0 and SDI = 0 immediately after the programming command.
The actual programming pulse occurs internally at the falling edge of CS* in the command following the
command in which Zp = logic 1.
The write command can be used to preview the trim bits as long as Zp is logic 0.
Examples:
The bit field B[5:0] can be programmed while the A[2:0] bit field is "000", or vice versa. For example the
total SDI bit pattern could be 10 000 001100 0000 1. This would permanently set the B[5:0] bit field to
001100 but the filter setting could still be subsequently changed by a different write command, either in
preview or programming.
The SDI bit pattern 10 010 010000 0000 0 would set the filter time constant to 3T and the full scale field
to 010000 as a preview, without making it permanent (because bit Zp = 0).
If the sample interval T = 1 mS and A[2:0] = 001 then the effective bandwidth would be 1/(2*3.14*1e-3) =
159 Hz. For this condition, if the steady state output was 2000 counts and a step input was applied that
would drive the output to 3000 counts then the digital output response would be 2000, 2500, 2750, 2875,
2937, 2968, 2984, 2992, 2996, 2998, 2999, 2999, 3000.
MX8682
Drawing No. 0868209
5
03/03/08
www.claremicronix.com
FPGA/CPLD
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