Product Brief
PE42556 Flip Chip
For full datasheet, please visit
psemi.com.
Product Description
The PE42556 RF switch is designed for use in Test/ATE,
cellular and other wireless applications. This broadband
general purpose switch maintains excellent RF performance
and linearity from 9 kHz through 13500 MHz. The PE42556
integrates on-board CMOS control logic driven by a single-
pin, low voltage CMOS control input. It also has a logic
select pin which enables changing the logic definition of the
control pin. Additional features include a novel user defined
logic table, enabled by the on-board CMOS circuitry. The
PE42556 also exhibits excellent isolation of 26 dB at 13500
MHz, fast settling time, and is offered in a tiny Flip Chip
package.
The PE42556 is manufactured on Peregrine’s UltraCMOS
®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Features
UltraCMOS
®
SPDT RF Switch
9 kHz - 13500 MHz
HaRP™ technology enhanced
Eliminates gate lag
No insertion loss or phase drift
Fast settling time
Next Gen 0.25
μm
process technology
Single-pin 3.3V CMOS logic control
High isolation: 26 dB@ 13.5 GHz
Low insertion loss: 1.7 dB @ 13.5 GHz
P1dB: 33 dBm typical
Return loss: 13 dB @ 13.5 GHz (typ)
IIP3: +56 dBm typical
High ESD: 4kV HBM
Absorptive switch design
Flip Chip packaging
Figure 1. Functional Diagram
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Figure 2. Die Photo (Bumps Up)
Flip Chip Packaging
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71-0031
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Page 1 of 9
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PE42556
Product Brief
Table 1. Electrical Specifications:
Temp = 25°C, V
DD
= 3.3V
Parameter
Operation Frequency
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
76.5
43.5
30.0
24.0
15.5
72.5
39.0
31.5
27.0
21.5
Condition
Min
9 kHz
0.85
0.92
0.98
1.07
1.74
88.5
46.0
31.5
25.5
17.5
84.0
40.5
33.0
30.5
26.5
Typ
Max
13500 MHz
0.93
1.06
1.23
1.41
2.65
Unit
As shown
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
10.0
13.5
4.0
µs
µs
µs
dBm
dBm
dBm
Insertion Loss
Isolation – RF1 to RF2
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75.5
39.5
31.5
27.5
21.0
Isolation – RFC to RF1
Isolation – RFC to RF2
Return Loss
Settling Time
Switching Time
Input 1 dB
Compression
1,2
Input IP3
1
Input IP2
1
50% CTRL to 0.05 dB final value (-40 to +85 °C) Rising Edge
50% CTRL to 0.05 dB final value (-40 to +85 °C) Falling Edge
50% CTRL to 90% or 10% of final value (-40 to +85 °C)
13500 MHz
13500 MHz
13500 MHz
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Notes: 1. Linearity and power performance are derated at lower frequencies (< 1 MHz)
2. Please refer to Maximum Operating Pin (50Ω) in
Table 3
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87.0
41.0
33.0
30.5
26.0
22.5
22.0
17.0
16.0
13.0
8.5
9.5
3.3
33
56
107.5
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 9
Document No. DOC-50245-2
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UltraCMOS
®
RFIC Solutions
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PE42556
Product Brief
Figure 3. Bump Configuration (Bumps Up)
Flip Chip Packaging
Vdd
CTRL
Vss
Table 4. Absolute Maximum Ratings
Parameter/Condition
Power supply voltage
Voltage on any input except
V
I
for CTRL and LS inputs
V
CTRL
Voltage on CTRL input
Voltage on LS input
V
LS
T
ST
Storage temperature range
Operating temperature range
T
OP
9 kHz
≤
1 MHz
P
IN1
(50Ω)
1 MHz
≤
13.5 GHz
ESD voltage (HBM)
2
V
ESD
ESD voltage (Machine Model)
Symbol
V
DD
Min
-0.3
-0.3
Max
4.0
V
DD
+
0.3
4.0
4.0
150
85
Fig. 4,5
30
4000
300
Unit
V
V
V
V
°C
°C
dBm
dBm
V
V
11
LS
12
D-GND
1
D-GND
10
GND
13
DGND
2
GND
9
RF1
14
3
RF2
-65
-40
8
GND
RFC
4
GND
7
6
5
Notes: 1. Please consult
Figures 4
and
5
(low-frequency graphs) for
recommended low-frequency operating power level.
2. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
1
2, 13, 14
3, 5, 7, 9
4
6
8
10
11
12
V
SS
D-GND
GND
RF2
RFC
RF1
LS
V
DD
CTRL
Negative supply voltage or GND
connection (Note 1)
Digital Ground
Ground
RF Port 2
RF Common
RF Port 1
Logic Select - Used to determine the
definition for the CTRL pin (see
Table 5)
Nominal 3.3V supply connection
CMOS logic level
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Electrostatic Discharge (ESD) Precautions
®
When handling this UltraCMOS device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Note 1: Use VSS (bump 1, VSS = -VDD) to bypass and disable internal negative
voltage generator. Connect VSS (bump 1) to GND (VSS = 0V) to enable
internal negative voltage generator.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
®
Table 3. Operating Ranges
Parameter
V
DD
Positive Power Supply
Voltage
V
DD
Negative Power Supply
Voltage
I
DD
Power Supply Current
(V
ss
= -3.3V, V
DD
= 3.0 to
3.6V, -40 to +85 °C)
I
DD
Power Supply Current
(V
ss
= 0V, V
DD
= 3.0 to 3.6V,
-40 to +85 °C)
I
SS
Negative Power Supply
Current
(V
ss
= -3.3V, V
DD
= 3.0 to
3.6V, -40 to +85 °C)
Control Voltage High
Control Voltage Low
P
IN
RF Power In
1
(50Ω):
9 kHz
≤
1 MHz
1 MHz
≤
13.5 GHz
0.7xV
DD
Min
3.0
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Table 5. Control Logic Truth Table
Unit
V
V
μA
LS
0
0
1
1
CTRL
0
1
0
1
RFC-RF1
off
on
on
off
RFC-RF2
on
off
off
on
ot
Typ
3.3
Max
3.6
N
-3.6
-3.3
8.0
-3.0
12.5
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
21.5
29.0
μA
Spurious Performance
The typical spurious performance of the PE42556 is
-116 dBm when VSS = 0V (bump 1 = GND). If further
improvement is desired, the internal negative voltage
generator can be disabled by setting VSS = -VDD.
-18.0
-24.0
μA
V
0.3xV
DD
Fig. 4,5
30
V
dBm
dBm
Switching Frequency
The PE42556 has a maximum 25 kHz switching rate
when the internal negative voltage generator is used
(bump1 = GND). The rate at which the PE42556 can
be switched is only limited to the switching time
(Table
1)
if an external negative supply is provided
(bump1 = VSS).
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
Note 1: Please consult Figures 4 and 5 (low-frequency graphs) for recommended
low-frequency operating power level.
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Bump No.
Bump
Name
Description
s
Table 2. Bump Descriptions
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
PE42556
Product Brief
Low Frequency Power Handling: Z
L
= 50Ω
Figure 4
provides guidelines of how to adjust the
Vdd and Input Power to the PE42556 device. The
upper limit curve represents the maximum Input
Power vs Vdd recommended for this part at low
frequencies only. Please consult
Table 3
for the
1 MHz
≤
13.5 GHz range.
Figure 4. Maximum Operating Power Limit
vs. Vdd and Input Power @ 9 kHz
Upper Power Limit
8
6
Input Power (dBm)
Operating Power Offset (dB)
25
Figure 5
shows how the power limit in
Figure 4
will
increase with frequency. As the frequency
increases, the contours and Maximum Power
Limit Curve will increase with the increase in
power handling shown on the curve.
Figure 5. Operating Power Offset vs.
Frequency (Normalized to 9 kHz)
Power Handling Scaling with Frequency
30
4
2
0
-2
-4
-6
-8
-10
-12
2.9
3
3.1
3.2
3.3
3.4
3.5
Vdd (V)
ew
3.6
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15
10
5
0
1
10
Freq (kHz)
100
1000
20
fo
To allow for sustained operation under any load VSWR condition, max power
should be kept 6dB lower than max power in 50 Ohm.
rn
Power Handling Examples
Example 1: Maximum power handling at 100 kHz,
Z = 50 ohms, VSWR 1:1, and Vdd = 3V
The power handling offset for 100 kHz from
Fig. 5
is 7 dB
The max power handling at Vdd = 3V is 5.5 dB
from
Fig. 4
Derate power under mismatch conditions
Total maximum power handling for this
example is 7 dB + 5.5 dB = 12.5 dBm
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Document No. DOC-50245-2
│
UltraCMOS
®
RFIC Solutions
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psemi.com
for full version of datasheet
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 9
s
PE42556
Product Brief
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine's PE42556 (dual
use with PE42554). The RF Common port is
connected through a 50 ohm transmission line via
the top SMA connector, J1. RF1 and RF2 are
connected through 50 ohm transmission lines via
SMA connectors J3, and J2, respectively. A
through 50 ohm transmission line is available via
SMA connectors J4 and J5. This transmission line
can be used to estimate the loss of the PCB over
the environmental conditions being evaluated.
The board is constructed of a four metal layers
with a total thickness of 62 mils. The top and
bottom layers are ROGERS RO4003 material with
an 8 mil core and Er = 3.55. The middle layers
provide ground for the transmission lines. The RF
transmission lines were designed using a coplanar
waveguide with ground plane model using a trace
width of 15 mils, and trace gaps of 10 mils.
Figure 6. Evaluation Board Layouts
Peregrine Specification 101/0402
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General Comments
--
Transmission lines connected to J1, J2, and J3 should
have exactly the same electrical length.
The path from J2 to J3 including the distance through the part
should have the same length as J4 and J5 and be in parallel to
J4 to J5.
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Figure 7. Evaluation Board Schematic
Peregrine Specification 102/0478
J9
HEADER, 12 PIN
1
3
5
7
9
11
NOTES:
1. USE 101-0402-02 PCB
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1
12
11
10
U1
PE42554
RF1
8
gn
X
CTL
LS
NC
VDD
VSS
GND
GND
GND
GND
GND
GND
GND
s
2
4
6
8
10
12
2
1
J3
J1
1
2
6
RFC
RF2
VSS
CTL
VDD
LS
4
2
1
G0
G1
G2
G4
G5
G6
G7
J2
2
3
5
7
9
13
14
J4
1
2
2
1
J5
Document No. DOC-50245-2
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