CT2565
Bus Controller, Remote Terminal and BUS Monitor
FOR MIL-STD-1553B
Features
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Second Source Compatible to the BUS-65600
RTU implements all dual redundant mode codes
Selective mode code illegalization available
16 bit microprocessor compatibility
BC checks status word for correct address and set flags
RTU illegal mode codes externally selectable
16 bit µProcessor compatibility
DMA handshaking for subsystem message transfers
MIL-PRF-38534 compliant circuits available
DESC SMD #5962–88585 Pending
Packaging – Hermetic Metal
• 78 Pin, 2.1" x 1.87" x .25" Plug-In type package
• 82 Lead, 2.2" x 1.61" x .18" Flat package
CIRCUIT TECHNOLOGY
www.aeroflex.com
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ISO
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General Description
The CT2565 is a dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT), and
Bus Monitor, (BM) Bus packaged in a 1.9" x 2.1" hermetic hybrid. It provides all the functions
required to interface a MIL-STD-1553 dual redundant serial data bus transceiver, (Aeroflex's
ACT4487 for example) and a subsystem parallel three-state data bus. Utilizing a custom monolithic
IC, the CT2565 provides selectable operation as a Bus Controller, Remote Terminal or a Bus
Monitor (BM).
The CT2565 is compatible with most µprocessors. It provides a 16 bit three-state parallel data bus
and uses direct memory access (DMA type) handshaking for subsystem transfers. All message
transfer timing as well as DMA and control lines are provided internally. Subsystem overhead
associated with message transfers is therefore minimized. Interface control lines are common for
both BC and RT operation.
The CT2565 features the capability for implementing all dual redundant MIL-STD-1553 mode
codes. In addition, any mode code may (optional) be illegalized through the use of an external
(200ns access time) PROM. Complete error detection capability is provided, for both BC and RTU
operation. Error detection includes: response time-out, inter message gaps, sync, parity,
Manchester, word count and bit count. The CT2565 complies with all the requirements of
MIL-STD-1553.
The hybrid is screened in accordance with the requirements of MIL-STD-883 and operates over the
full military temperature range of -55°C to +125°C.
eroflex Circuit T
echnology
– Data Bus Modules For The Future © SCDCT2565 REV B 8/10/99
STATUS INPUTS
Aeroflex Circuit Technology
RTADDR
DBACCEPT
SSFLAG
SERREQ
SSERR
SSBUSY
MODE CODE CONTROL
CH A
CONTROL
REMOTE
TERMINAL
LOGIC
TXINH A
TXDATA A
TXDATA A
RXDATA A
RXDATA A
CH A
ENCODE/
DECODE
WC0-WC4
T/R
LMC
ILLCMD
I/O0 - I/O16
DATA BUS
DATA
BUFFERS
BUFENA
R/W
EN
2
CH B
CONTROL
CONTROL BUS
BUS
CONTROLLER
LOGIC
I/O BUS
I/O LOGIC
BUFFERS
TXINH
TXDATA
TXDATA
RXDATA
RXDATA
B
B
B
B
B
CH B
ENCODE/
DECODE
RTADDR
RTADR0
RTADR1
RTADR2
RTADR3
RTADR4
RTADRP
RTADDR
PARITY
CHECKER
BUSREQ
BUSGRNT
BUSACK
TIMEOUT
SOM
EOM
INCMD
CS
OE
WR
TESTIN
TESTOUT
RT/BC
MT
BCSTART
CHA/CHB
LOOPERR
MSGERR
STATERR
LWORD
HSFAIL
STATEN
BITEN
NBGRNT
ADRINC
NODT
BSCTRCV
12MHz
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Figure 1 – CT2565 Block Diagram
Values at nominal Power Supply Voltages unless otherwise specified
PARAMETER
Logic
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
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*
I
OH
*
C
IN
(f = 1MHz)
C
OUT
(f = 1MHz)
Power Supply
+5VDC
Tolerances
Supply Current
Internal Decoupling
Temperature Range
Operating (Case)
Storage
Physical Characteristics
Size
78 pin DDIP
82 pin flatpack
Weight
VALUE
2.0 min
0.8 max
3.7 min
0.4 max
±100 max
-0.4 max
±1.2 max
±0.4 max
20 max
20 max
UNITS
V
V
V
V
µA
mA
mA
mA
pF
pF
±10 max
50 typ (70 max)
1.5 typ
−
55 to +125
−
65 to +150
%
mA
µF
°C
°C
1.9 x 2.10 x 0.25
(48.30 x 53.34 x 6.35)
1.6 x 2.19 x 0.15
(40.64 x 55.63 x 3.81)
1.7 (48)
in
(mm)
in
(mm)
oz (g)
* I
OL
and I
OH
parameters are indicated for all logic outputs except Data Bus (DB0 – DB15) which are ±5mA for
both parameters.
Table 1 – CT2565 Specifications
GENERAL
The CT2565 uses a custom CMOS ASIC for
protocol logic and I/O buffering to provide low
power dissipation in its small package.
The CT2565 performs a continuous on-line
Built-In-Test (BIT); in this test the last transmitted
word of each message transfer is wrapped
around through the active receiver channel and
verified against the captured encoded word. A
user-defined loop test under subsystem control
can also be implemented. Numerous error flags
are provided to the subsystem including
message error, status error, response time out
and loop test error.
An external 12 MHz, TTL clock connected to Pin
39 is required.
Where appropriate, references to signal names
and their associated pin numbers for the 78 pin
Aeroflex Circuit Technology
DDIP package are made throughout this
document. For flatpack model pin numbers, refer
to Table 10.
BC/RTU/MT Initialization
The CT2565 provides BC, RTU, and MT
operating modes.
The operating mode if
dynamically selectable through two static control
inputs as listed in Table 2. It is recommended
that a master RESET signal be issued (80ns min)
prior to mode selection to clear the internal
registers.
MIL-STD-1553 Word Types
Figure 2 illustrates the three MIL-STD-1553 word
types: Command, Data, and Status.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
BIT TIMES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
COMMAND WD
SYNC
5
REMOTE TERMINAL
ADDRESS
T/R
5
SUBADDRESS
MODE
16
5
DATA WORD
COUNT/MODE CODE
1
P
DATA WORD
SYNC
STATUS WORD
SYNC
5
REMOTE TERMINAL
ADDRESS
1
1
1
P
3
RESERVED
PARITY
TERMINAL FLAG
DYNAMIC BUS
CONTROL
ACCEPTANCE
SUBSYSTEM FLAG
BUSY
BROADCAST
COMMAND RCVD
1
1
1
1
1
1
DATA
1
MESSAGE ERROR
INSTRUMENTATION
SERVICE REQUEST
Note: T/R – Transmit/Receive, P – Parity
Figure 2 – MIL-STD-1553 Word Types
RT/BC
(PIN 1)
0
1
0
MT
(PIN 2)
1
1
0
MODE
BC
RT
MT
triggers an address increment (ADRINC pin) low
output pulse used to increment the subsystem
memory address for successive transfers.
BC OPERATION
In the BC mode, the CT2565 initiates all
MIL-STD-1553 data and control message
transfers. Figure 3 details specific message
transfer flow and Table 3 lists subsystem memory
allocation. The subsystem, or host processor,
must provide a CT2565 protocol Control Word
(See Figure 4) and MIL-STD-1553 command and
data words. The CT2565 will transfer the RTU
status response and provide message transfer
validation during an active transfer. All parallel
word transfers occur in the form of a DMA
(request-grant-acknowledge) handshake with
memory read or operation as shown in Figures 5
and 6.
Command Transfer
In the BC mode pulse BCSTART (pin 41) low.
Following the pulse, the CT2565 will initiate a
DMA handshake and memory read for; the
control, word, command word(s) and up to 32
data words. No handshake timeout is enforced in
the BC mode (CT2565) remains idle during
BUSREQ to BUSGRNT), however 1553 protocol
must be maintained.
Note that commands are named from the BC's
point-of-view (for example, a TRANSMIT CMD
indicates the addressed RTU must transmit data).
Table 2 – Operating Modes
DMA - Type Handshake
All BC and RT word transfers are preceded by a
request-grant-acknowledge
format
DMA
handshake procedure. Timing information is
provided in BC, RTU and MT sections.
In MT mode, the 1553 transmission is transferred
along with an identification Word using a single
DMA handshake containing two memory-write
operations. The DMA format requires that the
subsystem provide a bus grant (BUSGRNT pin
45) low within a timeout period. Note that
BUSGRNT should be set to logic "1" before
another bus request (BUSREQ) is issued.
Memory Read/Write
With the single exception of an RT command
word transfer, all subsystem transfers take the
form of a static memory read or write. A low
pulse on both the chip select (CS) and output
enable (OE) or a low pulse on CS and write
enable (WE) (pins 17, 18 and 44 respectively)
indicates data is valid on the parallel data bus for
the duration of the pulse. The rising edge of CS
Aeroflex Circuit Technology
4
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
RECEIVE
Control Word
Receive Command
Data 1
•
•
Last Data
Looped Data Word
RTU Status
TRANSMIT
Control Word
Transmit Command
Looped Command Word
RTU Status
Data 1
•
•
Last Data
Table 3 – BC Memory Allocation
Loop Test
Upon receipt from the subsystem, the last word
to be transmitted within a given message
transfer (command or Data word) is stored in a
CT2565 internal register.
As this word is
transmitted to the 1553 bus, it is looped back
through the active receiver channel for auto-BC,
Short Loop verification. A LOOPERR (.5us typ)
low pulse indicates a mismatch between the
stored and looped word. The CT2565 also
initiates a handshake with a memory write to the
subsystem for user-defined, "long loop"
(subsystem, CT2565, subsystem) verification.
Note that both short and long loop testing are
initiated for all transfers (on the last word
transmitted to 1553). Subsystems response to
use Long Loop Test is to compare the loaded
word to what was looped back into memory.
15
NOT USED
BUS CHANNEL A/
B
NOT USED
MASK BROADCAST BIT
NOT USED
MODE CODE
BROADCAST
RT-RT
8
0
BIT
BUS CHANNEL A/B
DEFINITION
When logic "1" transmits over 1553 Bus A.
When logic "0" transmits over 1553 Bus B
(See note)
Always set to "0"
Command Word count field signifies mode code type
Multiple RTU’s addressed, no status word expected
When set, RTU(b) transmits, RTU(a) receives. Both RTU Status Words
are validated and sent to subsystem.
MASK BROADCAST BIT
MODE CODE
BROADCAST
RT-RT
Note: Messages-transmission (routing) status pin (pin 16, Chan A/B) becomes active after loading the control word and command word
respectively. The signal is cleared by RESET or EOM low.
Figure 4 – BC Control Word
Aeroflex Circuit Technology
5
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
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