CAT93C56/57
(Die Rev. E)
2K-Bit Microwire Serial EEPROM
FEATURES
I
High speed operation: 1MHz
I
Low power CMOS technology
I
1.8 to 6.0 volt operation
I
Selectable x8 or x16 memory organization
I
Self-timed write cycle with auto-clear
I
Hardware and software write protection
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
I
Power-up inadvertant write protection
I
1,000,000 Program/erase cycles
I
100 year data retention
I
Commercial, industrial and automotive
temperature ranges
I
Sequential read
I
“Green” package option available
DESCRIPTION
The CAT93C56/57 are 2K-bit Serial EEPROM memory
devices which are configured as either registers of 16
bits (ORG pin at V
CC
) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C56/57 are manufactured
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The devices are designed to endure
1,000,000 program/erase cycles and has a data reten-
tion of 100 years. The devices are available in 8-pin DIP,
SOIC, TSSOP and 8-pad TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
FUNCTIONAL SYMBOL
SOIC Package (J,W)
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
V
CC
ORG
CS
SK
NC
DI
DO
SOIC Package (S,V)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
SOIC Package (K,X)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
GND
PIN FUNCTIONS
Pin Name
CS
SK
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
Memory Organization
No Connection
TSSOP Package (U,Y)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
DI
DO
V
CC
GND
TDFN Package (RD4, ZD4)
VCC
8
NC
7
ORG
6
GND
5
1
CS
2
SK
3
DI
4
DO
ORG
NC
Bottom View
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1088, Rev. N
CAT93C56/57
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............. -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V
I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V
I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V
I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V
I
OH
= -100µA
V
CC
- 0.2
2.4
0.2
-0.1
2
0
V
CC
x 0.7
0
Min
Typ
Max
3
500
10
10
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+1
0.4
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Doc. No. 1088, Rev. N
2
CAT93C56/57
PIN CAPACITANCE
Symbol
C
OUT(2)
C
IN(2)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
=0V
V
IN
=0V
Min
Typ
Max
5
5
Units
pF
pF
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Device
Type
93C56
(1)
93C57
93C56
(1)
93C57
93C56
(1)
93C57
93C56
(1)
93C57
93C56
(1)
93C57
93C56
(1)
93C57
93C56
(1)
93C57
Start
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address
Opcode
10
10
11
11
01
01
00
00
00
00
00
00
00
00
x8
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
A7-A0
11XXXXXXX
11XXXXXX
00XXXXXXX
00XXXXXX
10XXXXXXX
10XXXXXX
01XXXXXXX
01XXXXXX
Data
x8
x16
Comments
Read Address AN– A0
Clear Address AN– A0
D7-D0
D7-D0
D15-D0 Write Address AN– A0
D15-D0
Write Enable
Write Disable
Clear All Addresses
D7-D0
D7-D0
D15-D0 Write All Addresses
D15-D0
x16
A7-A0
A6-A0
A7-A0
A6-A0
A7-A0
A6-A0
11XXXXXX
11XXXXX
00XXXXXX
00XXXXX
10XXXXXX
10XXXXX
01XXXXXX
01XXXXX
A.C. CHARACTERISTICS
Limits
V
CC
=
1.8V-6V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
250
DC
C
L
= 100pF
(3)
Test
Conditions
Min
200
0
400
400
1
1
400
10
0.5
0.5
0.5
0.5
500
DC
Max
V
CC
=
2.5V-6V
Min
100
0
200
200
0.5
0.5
200
10
0.25
0.25
0.25
0.25
1000
Max
V
CC
=
4.5V-5.5V
Min
50
0
100
100
0.25
0.25
100
10
Max
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1088, Rev. N
CAT93C56/57
POWER-UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C56/57 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 10-bit instructions for 93C57; seven 11-bit
instructions for 93C56 control the reading, writing and
erase operations of the device. When organized as X8,
seven 11-bit instructions for 93C57; seven 12-bit in-
structions for 93C56 control the reading, writing and
erase operations of the device. The CAT93C56/57
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high)
and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high indi-
cates that the device is ready for the next instruction. If
necessary, the DO pin may be placed back into a high
impedance state during chip select by shifting a dummy
“1” into the DI pin. The DO pin will enter the high
impedance state on the falling edge of the clock (SK).
Placing the DO pin into the high impedance state is
recommended in applications where the DI pin and the
4
DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address
(93C57)/ 8-bit address (93C56) (an additional bit when
organized X8) and for write operations a 16-bit data field
(8-bit for X8 organizations).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/
57 will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (t
PD0
or t
PD1
).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Doc. No. 1088, Rev. N
CAT93C56/57
Figure 1. Sychronous Data Timing
tSKHI
SK
tDIS
DI
tCSS
CS
tDIS
DO
tPD0,tPD1
DATA VALID
tCSMIN
VALID
VALID
tDIH
tSKLOW
tCSH
Figure 2. Read Instruction Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS
Don't Care
AN
DI
1
1
0
AN–1
A0
DO
HIGH-Z
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D 7 . . . D0
Address + 2
D15 . . . D0
or
D 7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. Write Instruction Timing
SK
tCSMIN
CS
AN
DI
1
0
1
tSV
DO
HIGH-Z
tEW
BUSY
READY
HIGH-Z
tHZ
AN-1
A0
DN
D0
STATUS
VERIFY
STANDBY
5
Doc. No. 1088, Rev. N
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
