Clock OSC
SG3225EAN
SG3225EAN 250.000000MHz KEGA
Product name
X1G0042510104xx
Product Number / Ordering code
Please refer to the 9.Packing information about xx (last 2 digits)
Output waveform
LV-PECL
Pb free / Complies with EU RoHS directive
Reference weight Typ. 25 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.3
-40
-0.3
Typ.
-
-
-
Max.
+4
+125
Vcc+0.3
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST or OE Terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Disable current
Symmetry
Output voltage(LV-PECL)
Output load condition(ECL)
Input voltage
Rise time
Fall time
Start-up time
Jitter
Min.
2.25
-40
-30
-
-
-
45
Vcc-1.0
-
-
70% Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Typ.
Max.
Unit
MHz
V
ºC
x10
-6
mA
mA
mA
%
V
V
Ω
Conditions / Remarks
-
-
-
OE = Vcc , L_ECL = 50 ohm
-
OE=GND
At output crossing point
-
-
Terminated to Vcc - 2.0V
OE Terminal
OE Terminal
Phase jitter
Phase noise
f0
Vcc
T_use
f_tol
Icc
I_std
I_dis
SYM
V
OH
V
OL
L_ECL
V
IH
V
IL
t
r
tf
t_str
t
DJ
T
RJ
t
RMS
t
p-p
t
acc
t
PJ
L(f)
Frequency aging
f_age
250.0000
-
3.63
-
+85
-
30
-
65
-
-
-
20.0
-
55
-
-
-
Vcc-1.62
50
-
-
-
-
30% Vcc
-
0.35
-
0.35
-
3
13.1
-
2.8
-
5.7
-
33.6
-
6.7
-
0.59
-
-
-
-80
-
-105
-
-117
-
-126
-
-129
-
-126
-
-
5
ps
ps
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-6
At 20% to 80% output swing
At 20% to 80% output swing
-
Deterministic Jitter Vcc=2.5V
Random Jitter Vcc=2.5V
δ(RMS of total distribution) Vcc=2.5V
Peak to Peak Vcc=2.5V
Vcc=2.5V
Off set Frequency: 12kHz to 20MHz Vcc=2.5V
-
Off set 10Hz Vcc=2.5V
Off set 100Hz Vcc=2.5V
Off set 1kHz Vcc=2.5V
Off set 10kHz Vcc=2.5V
Off set 100kHz Vcc=2.5V
Off set 1MHz Vcc=2.5V
x10 /Year
@+25ºC first year
1 Page
3.Test circuit
1) To observe waveform and current (case 1)
Vcc
+3.3 V
________
A
By-pass
capacitor 2
Power
supply 2
Vcc
OUT
OUT
130 Ω
130 Ω
Test Point
OE
OE pin
NC
GND
82 Ω
By-pass
capacitor 1
Test Point
82 Ω
________
* The lines from OUT and OUT pin are same length.
* To measure the disable current, OE pin is connected to GND
2) To observe waveform and current (case 2)
A
+3.3 V
________
Test Point
OUT
OUT
50 Ω
Test Point
50 Ω
Vcc-2 V
By-pass
capacitor 2
Power
supply 2
Vcc
OE
OE pin
NC
GND
By-pass
capacitor 1
________
* The lines from OUT and OUT pin are same length.
* To measure the disable current, OE pin is connected to GND
3) Measurement condition
A) Oscilloscope
•Bandwidth should be 5 times higher than DUT’s output frequency (4 GHz).
•Probe ground should be placed closely from test point and lead length should be as short as possible.
B) By-pass capacitor 1 (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.
C) By-pass capacitor 2 (approx. 10 μF) places closely between power supply terminals on the board.
D) Use the current meter whose internal impedance value is small.
E) Power supply
• Start up time (0 Vg90 %Vcc) of power source should be more than 150 μs and
slew rate should be less than 19.8 mV/μs.
• Impedance of power supply should be as low as possible.
2 Page
4.Timing chart
Vcc
80 % of amplitude
tr
tf
________
OUT
20 % of amplitude
Vcc-2 V
OUT
GND
tw
SYM = tw / t
t
5.External dimensions
(Unit: mm)
6.Footprint(Recommended)
(Unit: mm)
#6
#5
#4
#1
#2
#3
2.58
To maintain stable operation, provide a 0.01uF to 0.1uF
by-pass capacitor at a location as near as possible to the
power source terminal of the crystal product (between Vcc
- GND).
7.Reflow profile
Reflow condition (Follow of JEDEC STD-020D.01)
Temperature[C]
300
250
200
150
100
50
Time
+25CtoPeak
0
60
120 180 240 300 360 420 480 540 600 660 720 780
Time[s]
;+217C
Tsmax;+200C
TL
TP
;+260C
+255C
Avg.
Ramp-up
3
C/sMax.
tp
;20sto40s
tL
60sto150s
(+217Cover)
Ramp-down
6C/sMax.
Tsmin;+150C
ts
60sto180s
(+150Cto+200C)
3 Page
1.85
1.05
0.82
0.86
8.Example of schematic layout
This figure shows an example of this product’s application schematic.
As with any high speed analog circuitry, the power supply pins for this device are vulnerable to
noise. In order to achieve optimum jitter performance, power isolation with filter device is
required for power supply pins.
In order to achieve best performance of the power isolation filter, it is recommended that the
filter composing devices is placed on the device side of the PCB as close to the power pins as
possible. The component value of this filter is just an example, it may have to be adjusted.
4 Page
* By-pass capacitor (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.
* By-pass capacitor (approx. 10 μF) places closely between power supply terminals on the board.
* Please design the two output lines by characteristic impedance 50 Ω and same length, and try
to make the output lines as short as possible.
* Terminators place near the input device.
9.Packing information
[ 1 ]Product number last 2 digits code(xx) description
The recommended code is "00"
Code
13
14
00
Condition
500pcs / Reel
1000pcs / Reel
2000pcs / Reel
X1G0042510104xx
Code
01
11
12
Condition
Any Q'ty vinyl bag(Tape cut)
Any Q'ty / Reel
250pcs / Reel
5 Page
FPGA/CPLD
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